pc.h

VxWorks 5.4嵌入式操作系统, Tornado II开发平台BSP包的移植

#define SRAM0_MEM_LENGTH	0x100000
#define SRAM1_MEM_START		0xd9000	/* mem for SRAM1 */
#define SRAM1_MEM_STOP		0xd9fff
#define SRAM1_MEM_LENGTH	0x100000
#define SRAM2_MEM_START		0xda000	/* mem for SRAM2 */
#define SRAM2_MEM_STOP		0xdafff
#define SRAM2_MEM_LENGTH	0x100000
#define SRAM3_MEM_START		0xdb000	/* mem for SRAM3 */
#define SRAM3_MEM_STOP		0xdbfff
#define SRAM3_MEM_LENGTH	0x100000
#define ELT0_IO_START		0x260	/* io for ELT0 */
#define ELT0_IO_STOP		0x26f
#define ELT0_INT_LVL		0x05
#define ELT0_INT_VEC		(INT_NUM_IRQ0 + ELT0_INT_LVL)
#define ELT0_NRF		0x00
#define ELT0_CONFIG		0	/* 0=EEPROM 1=AUI  2=BNC  3=RJ45 */
#define ELT1_IO_START		0x280	/* io for ELT1 */
#define ELT1_IO_STOP		0x28f
#define ELT1_INT_LVL		0x09
#define ELT1_INT_VEC		(INT_NUM_IRQ0 + ELT1_INT_LVL)
#define ELT1_NRF		0x00
#define ELT1_CONFIG		0	/* 0=EEPROM 1=AUI  2=BNC  3=RJ45 */

/* parallel port (LPT) */

#define LPT0_BASE_ADRS		0x3bc
#define LPT1_BASE_ADRS		0x378
#define LPT2_BASE_ADRS		0x278
#define LPT_INT_LVL             0x07
#define LPT_INT_VEC             (INT_NUM_IRQ0 + LPT_INT_LVL)
#define LPT_CHANNELS		1

/* FEI PCI bus resources */

#define FEI0_MEMBASE0		0xea000000	/* memory base for CSR */
#define FEI0_MEMSIZE0		0x00001000	/* memory size for CSR, 4KB */
#define FEI0_MEMBASE1		0xfd100000	/* memory base for Flash */
#define FEI0_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define FEI0_IOBASE0		0xf400		/* IO base for CSR, 32Bytes */
#define FEI0_INT_LVL		0x0d		/* IRQ 11 */
#define FEI0_INT_VEC		(INT_NUM_IRQ0 + FEI0_INT_LVL)
#define FEI0_INIT_STATE_MASK	(VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
                                 VM_STATE_MASK_CACHEABLE)
#define FEI0_INIT_STATE		(VM_STATE_VALID | VM_STATE_WRITABLE | \
                                 VM_STATE_CACHEABLE_NOT) 
#define FEI1_MEMBASE0		0xfd200000	/* memory base for CSR */
#define FEI1_MEMSIZE0		0x00001000	/* memory size for CSR, 4KB */
#define FEI1_MEMBASE1		0xfd300000	/* memory base for Flash */
#define FEI1_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define FEI1_IOBASE0		0xf420		/* IO base for CSR, 32Bytes */
#define FEI1_INT_LVL		0x05		/* IRQ 5 */
#define FEI1_INT_VEC		(INT_NUM_IRQ0 + FEI1_INT_LVL)
#define FEI1_INIT_STATE_MASK    (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
                                 VM_STATE_MASK_CACHEABLE) 
#define FEI1_INIT_STATE         (VM_STATE_VALID | VM_STATE_WRITABLE | \
                                 VM_STATE_CACHEABLE_NOT)
#define FEI2_MEMBASE0		0xfd400000	/* memory base for CSR */
#define FEI2_MEMSIZE0		0x00001000	/* memory size for CSR, 4KB */
#define FEI2_MEMBASE1		0xfd500000	/* memory base for Flash */
#define FEI2_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define FEI2_IOBASE0		0xf440		/* IO base for CSR, 32Bytes */
#define FEI2_INT_LVL		0x0c		/* IRQ 12 */
#define FEI2_INT_VEC		(INT_NUM_IRQ0 + FEI2_INT_LVL)
#define FEI2_INIT_STATE_MASK    (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
                                 VM_STATE_MASK_CACHEABLE) 
#define FEI2_INIT_STATE         (VM_STATE_VALID | VM_STATE_WRITABLE | \
                                 VM_STATE_CACHEABLE_NOT)
#define FEI3_MEMBASE0		0xfd600000	/* memory base for CSR */
#define FEI3_MEMSIZE0		0x00001000	/* memory size for CSR, 4KB */
#define FEI3_MEMBASE1		0xfd700000	/* memory base for Flash */
#define FEI3_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define FEI3_IOBASE0		0xf460		/* IO base for CSR, 32Bytes */
#define FEI3_INT_LVL		0x09		/* IRQ 9 */
#define FEI3_INT_VEC		(INT_NUM_IRQ0 + FEI3_INT_LVL)
#define FEI3_INIT_STATE_MASK    (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
                                 VM_STATE_MASK_CACHEABLE) 
#define FEI3_INIT_STATE         (VM_STATE_VALID | VM_STATE_WRITABLE | \
                                 VM_STATE_CACHEABLE_NOT)


#define BT0_MEMBASE0		0xe4000000	/* memory base for CSR */
#define BT0_MEMSIZE0		0x00100000	/* memory size for CSR, 4KB */
#define BT0_MEMBASE1		0xe4100000	/* memory base for Flash */
#define BT0_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define BT0_IOBASE0		0xf460		/* IO base for CSR, 32Bytes */
#define BT0_INT_LVL		0x09		/* IRQ 9 */
#define BT0_INT_VEC		(INT_NUM_IRQ0 + FEI3_INT_LVL)
#define BT0_INIT_STATE_MASK    (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
                                 VM_STATE_MASK_CACHEABLE) 
#define BT0_INIT_STATE         (VM_STATE_VALID | VM_STATE_WRITABLE | \
                                 VM_STATE_CACHEABLE_NOT)

#define BT1_MEMBASE0		0xe4000000	/* memory base for CSR */
#define BT1_MEMSIZE0		0x00100000	/* memory size for CSR, 4KB */
#define BT1_MEMBASE1		0xe4100000	/* memory base for Flash */
#define BT1_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define BT1_IOBASE0		0xf460		/* IO base for CSR, 32Bytes */
#define BT1_INT_LVL		0x09		/* IRQ 9 */
#define BT1_INT_VEC		(INT_NUM_IRQ0 + FEI3_INT_LVL)
#define BT1_INIT_STATE_MASK    (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
                                 VM_STATE_MASK_CACHEABLE) 
#define BT1_INIT_STATE         (VM_STATE_VALID | VM_STATE_WRITABLE | \
                                 VM_STATE_CACHEABLE_NOT)

#define BT2_MEMBASE0		0xe4000000	/* memory base for CSR */
#define BT2_MEMSIZE0		0x00100000	/* memory size for CSR, 4KB */
#define BT2_MEMBASE1		0xe4100000	/* memory base for Flash */
#define BT2_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define BT2_IOBASE0		0xf460		/* IO base for CSR, 32Bytes */
#define BT2_INT_LVL		0x09		/* IRQ 9 */
#define BT2_INT_VEC		(INT_NUM_IRQ0 + FEI3_INT_LVL)
#define BT2_INIT_STATE_MASK    (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
                                 VM_STATE_MASK_CACHEABLE) 
#define BT2_INIT_STATE         (VM_STATE_VALID | VM_STATE_WRITABLE | \
                                 VM_STATE_CACHEABLE_NOT)

#define BT3_MEMBASE0		0xe4000000	/* memory base for CSR */
#define BT3_MEMSIZE0		0x00100000	/* memory size for CSR, 4KB */
#define BT3_MEMBASE1		0xe4100000	/* memory base for Flash */
#define BT3_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define BT3_IOBASE0		0xf460		/* IO base for CSR, 32Bytes */
#define BT3_INT_LVL		0x09		/* IRQ 9 */
#define BT3_INT_VEC		(INT_NUM_IRQ0 + FEI3_INT_LVL)
#define BT3_INIT_STATE_MASK    (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
                                 VM_STATE_MASK_CACHEABLE) 
#define BT3_INIT_STATE         (VM_STATE_VALID | VM_STATE_WRITABLE | \
                                 VM_STATE_CACHEABLE_NOT)
/* key board (KBD) */

#define PC_XT_83_KBD		0	/* 83 KEY PC/PCXT/PORTABLE 	*/
#define PC_PS2_101_KBD		1	/* 101 KEY PS/2 		*/
#define KBD_INT_LVL		0x01
#define KBD_INT_VEC		(INT_NUM_IRQ0 + KBD_INT_LVL)

#define	COMMAND_8042		0x64
#define	DATA_8042		0x60
#define	STATUS_8042		COMMAND_8042
#define COMMAND_8048		0x61	/* out Port PC 61H in the 8255 PPI */
#define	DATA_8048		0x60	/* input port */
#define	STATUS_8048		COMMAND_8048

#define JAPANES_KBD             0
#define ENGLISH_KBD             1

/* beep generator */

#define DIAG_CTRL	0x61
#define BEEP_PITCH_L	1280 /* 932 Hz */
#define BEEP_PITCH_S	1208 /* 987 Hz */
#define BEEP_TIME_L	(sysClkRateGet () / 3) /* 0.66 sec */
#define BEEP_TIME_S	(sysClkRateGet () / 8) /* 0.15 sec */

/* Monitor definitions */

#define MONOCHROME              0
#define VGA                     1
#define MONO			0
#define COLOR			1
#define	VGA_MEM_BASE		(UCHAR *) 0xb8000
#define	VGA_SEL_REG		(UCHAR *) 0x3d4
#define VGA_VAL_REG             (UCHAR *) 0x3d5
#define MONO_MEM_BASE           (UCHAR *) 0xb0000
#define MONO_SEL_REG            (UCHAR *) 0x3b4
#define MONO_VAL_REG            (UCHAR *) 0x3b5
#define	CHR			2

/* change this to JAPANES_KBD if Japanese enhanced mode wanted */

#define KEYBRD_MODE             ENGLISH_KBD 

/* undefine this if ansi escape sequence not wanted */

#define INCLUDE_ANSI_ESC_SEQUENCE 

#define GRAPH_ADAPTER   VGA

#if (GRAPH_ADAPTER == MONOCHROME)

#define DEFAULT_FG  	ATRB_FG_WHITE
#define DEFAULT_BG 	ATRB_BG_BLACK
#define DEFAULT_ATR     DEFAULT_FG | DEFAULT_BG
#define CTRL_SEL_REG	MONO_SEL_REG		/* controller select reg */
#define CTRL_VAL_REG	MONO_VAL_REG		/* controller value reg */
#define CTRL_MEM_BASE	MONO_MEM_BASE		/* controller memory base */
#define COLOR_MODE	MONO			/* color mode */

#else /* GRAPH_ADAPTER = VGA */

#define DEFAULT_FG	ATRB_FG_BRIGHTWHITE
#define DEFAULT_BG	ATRB_BG_BLUE
#define DEFAULT_ATR	DEFAULT_FG | DEFAULT_BG
#define CTRL_SEL_REG	VGA_SEL_REG		/* controller select reg */
#define CTRL_VAL_REG	VGA_VAL_REG		/* controller value reg */
#define CTRL_MEM_BASE	VGA_MEM_BASE		/* controller memory base */
#define COLOR_MODE	COLOR			/* color mode */

#endif /* (ADAPTER == MONOCHROME) */

#endif	/* INCpch */