pc.h

VxWorks 5.4嵌入式操作系统, Tornado II开发平台BSP包的移植

/* pc.h - PC 386 header */

/*
modification history
--------------------
01z,17mar98,sbs  added definitions for dynamic mmu entries.
01y,12mar98,sbs  changed SCSI-2 definitions to device specific definitions. 
                 Added PCI configuration definitions and FEI specific 
                 definitions. 
01x,10jul97,dds  added SCSI-2 support.
01w,16jan97,hdn  added PCMCIA_SOCKS, PCMCIA_MEMBASE.
01v,03dec96,hdn  renamed PCI_FEIxxx to FEIxxx.
01u,20nov96,hdn  added support for PRO100B.
01t,01nov96,hdn  added support for PCMCIA.
01s,21oct96,hdn  added new configuration macros for LPT: LPT_xxx.
01r,12oct96,hdn  added support for ATA-2.  changed ATA[01]_CONFIG.
01q,03sep96,hdn  added the compression support.
01p,09aug96,hdn  renamed INT_VEC_IRQ0 to INT_NUM_IRQ0.
01o,19jul96,hdn  added support for ATA driver.
01n,25jun96,hdn  added support for TIMESTAMP timer.
01m,28may96,hdn  renamed PIT_INT_xxx to PIT0_INT_xxx.
01l,14jun95,myz  removed #include tyLib.h
01k,21oct94,hdn  deleted ENABLE_A20 macro.
01j,15oct94,hdn  added macros for LPT parallel driver.
01i,25apr94,hdn  moved a macro PC_KBD_TYPE to config.h.
01h,08nov93,vin  added support for pc console drivers.
01g,12oct93,hdn  added interrupt level macros.
01f,16aug93,hdn  added RTC related macros.
01e,03aug93,hdn  changed vectors for serial and timer.
01d,17jun93,hdn  updated to 5.1.
01c,07apr93,hdn  renamed compaq to pc.
01b,26mar93,hdn  deleted a macro CPU because it supports 386 and 486.
01a,15may92,hdn  written based on frc386 version.
*/

/*
This file contains IO address and related constants for the
PC 386.
*/

#ifndef	INCpch
#define	INCpch

#include "drv/intrCtl/i8259a.h"
#include "drv/timer/i8253.h"
#include "drv/timer/mc146818.h"
#include "drv/timer/timerDev.h"
#include "drv/timer/timestampDev.h"
#include "drv/hdisk/ideDrv.h"
#include "drv/fdisk/nec765Fd.h"
#include "drv/serial/pcConsole.h"
#include "drv/parallel/lptDrv.h"
#include "drv/pcmcia/pcmciaLib.h"
#include "drv/hdisk/ataDrv.h"
/*#include "drv/pci/pciConfigLib.h"*/

#undef	CAST
#define	CAST

#define TARGET_PC386

#define BUS		VME_BUS		/* XXX */

#define INT_NUM_IRQ0	0x20		/* vector number for IRQ0 */

#define	BOOTCODE_IN_RAM			/* for ../all/bootInit.c */

/* constant values in romInit.s */

#define ROM_IDTR	0xaf		/* offset to romIdtr  */
#define ROM_GDTR	0xb5		/* offset to romGdtr  */
#define ROM_GDT		0xc0		/* offset to romGdt   */
#define ROM_INIT2	0xf0		/* offset to romInit2 */
#define ROM_STACK	0x7000		/* initial stack pointer */
#define ROM_WARM_HIGH	0x10		/* warm start entry p */
#define ROM_WARM_LOW	0x20		/* warm start entry p */

/* programmable interrupt controller (PIC) */

#define	PIC1_BASE_ADR		0x20
#define	PIC2_BASE_ADR		0xa0
#define	PIC_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */

/* serial ports (COM1,COM2) */

#define	COM1_BASE_ADR		0x3f8
#define	COM2_BASE_ADR		0x2f8
#define	COM1_INT_LVL		0x04
#define	COM2_INT_LVL		0x03
#define	COM1_INT_VEC		(INT_NUM_IRQ0 + COM1_INT_LVL)
#define	COM2_INT_VEC		(INT_NUM_IRQ0 + COM2_INT_LVL)
#define	UART_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */
#define	N_UART_CHANNELS		2

/*
 * sysPhysMemDesc[] dummy entries:
 * these create space for updating sysPhysMemDesc table at a later stage
 * mainly to provide plug and play
 */

#define DUMMY_PHYS_ADDR         -1
#define DUMMY_VIRT_ADDR         -1
#define DUMMY_LENGTH            -1
#define DUMMY_INIT_STATE_MASK   -1
#define DUMMY_INIT_STATE        -1

#define DUMMY_MMU_ENTRY		{ (void *) DUMMY_PHYS_ADDR, \
                                  (void *) DUMMY_VIRT_ADDR, \
                                  DUMMY_LENGTH, \
                                  DUMMY_INIT_STATE_MASK, \
                                  DUMMY_INIT_STATE \
                                }

/* PCI device configuration definitions */

#define PCI_CFG_FORCE		0x1	/* force user specified configuration */
#define PCI_CFG_AUTO		0x2	/* VxWorks does auto configuration - 
                                           currently unavailable */ 
#define PCI_CFG_NONE		0x3	/* external agent does configuration */

/* PCI configuration type */

#define PCI_CFG_TYPE		PCI_CFG_NONE	/* specify PCI configuartion type */

/* AIC7880 PCI bus resources */

#define AIC7880_MEMBASE  	0xf5200000	
#define AIC7880_MEMSIZE		0x00001000	/* memory size for CSR, 4KB */
#define AIC7880_IOBASE		0xf800	
#define AIC7880_INT_LVL		0x0a
#define AIC7880_INT_VEC		(INT_NUM_IRQ0 + AIC7880_INT_LVL)
#define AIC7880_INIT_STATE_MASK (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
                                 VM_STATE_MASK_CACHEABLE)
#define AIC7880_INIT_STATE      (VM_STATE_VALID | VM_STATE_WRITABLE | \
                                 VM_STATE_CACHEABLE_NOT)

/* timer (PIT) */

#define	PIT_BASE_ADR		0x40
#define	PIT0_INT_LVL		0x00
#define	PIT0_INT_VEC		(INT_NUM_IRQ0 + PIT0_INT_LVL)
#define	PIT_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */
#define	PIT_CLOCK		1193180

/* real time clock (RTC) */

#define	RTC_INDEX		0x70
#define	RTC_DATA		0x71
#define	RTC_INT_LVL		0x08
#define	RTC_INT_VEC		(INT_NUM_IRQ0 + RTC_INT_LVL)

/* floppy disk (FD) */

#define FD_INT_LVL              0x06
#define FD_INT_VEC              (INT_NUM_IRQ0 + FD_INT_LVL)
#define FD_DMA_BUF_ADDR		0x2000	/* floppy disk DMA buffer address */
#define FD_DMA_BUF_SIZE		0x3000	/* floppy disk DMA buffer size */

/* hard disk (IDE) */

#define IDE_CONFIG		0x0	/* 1: uses ideTypes table */
#define IDE_INT_LVL             0x0e
#define IDE_INT_VEC             (INT_NUM_IRQ0 + IDE_INT_LVL)

/* hard disk (ATA) */

#define ATA0_IO_START0		0x1f0	/* io for ATA0 */
#define ATA0_IO_STOP0		0x1f7
#define ATA0_IO_START1		0x3f6
#define ATA0_IO_STOP1		0x3f7
#define ATA0_INT_LVL            0x0e
#define ATA0_INT_VEC            (INT_NUM_IRQ0 + ATA0_INT_LVL)
#define ATA0_CONFIG		(ATA_GEO_CURRENT | ATA_PIO_AUTO | \
				 ATA_BITS_16 | ATA_PIO_MULTI)
#define ATA1_IO_START0		0x170	/* io for ATA1 */
#define ATA1_IO_STOP0		0x177
#define ATA1_IO_START1		0x376
#define ATA1_IO_STOP1		0x377
#define ATA1_INT_LVL		0x09	/* 9 for PCIC. 5 for TCIC */
#define ATA1_INT_VEC		(INT_NUM_IRQ0 + ATA1_INT_LVL)
#define ATA1_CONFIG		(ATA_GEO_CURRENT | ATA_PIO_AUTO | \
				 ATA_BITS_16 | ATA_PIO_MULTI)
#define ATA_SEM_TIMEOUT		5       /* timeout for ATA sync sem */
#define ATA_WDG_TIMEOUT		5       /* timeout for ATA watch dog */

/* pcmcia (PCMCIA) */

#define PCMCIA_SOCKS		0x0	/* number of sockets. 0=auto detect */
#define PCMCIA_MEMBASE		0x0	/* mapping base address */
#define PCIC_BASE_ADR           0x3e0	/* Intel 82365SL */
#define PCIC_INT_LVL            0x0a
#define PCIC_INT_VEC            (INT_NUM_IRQ0 + PCIC_INT_LVL)
#define TCIC_BASE_ADR           0x240	/* Databook DB86082A */
#define TCIC_INT_LVL            0x0a
#define TCIC_INT_VEC            (INT_NUM_IRQ0 + TCIC_INT_LVL)
#define CIS_MEM_START           0xd0000	/* mapping addr for CIS tuple */
#define CIS_MEM_STOP            0xd3fff
#define CIS_REG_START           0xd4000	/* mapping addr for config reg */
#define CIS_REG_STOP            0xd4fff
#define SRAM0_MEM_START		0xd8000	/* mem for SRAM0 */
#define SRAM0_MEM_STOP		0xd8fff