pci.h

ucos_ii基础上加上网络功能

#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
#define PCI_PM_CTRL		4	/* PM control and status register */
#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER	7	/* (??) */
#define PCI_PM_SIZEOF		8

/* AGP registers */

#define PCI_AGP_VERSION		2	/* BCD version number */
#define PCI_AGP_RFU		3	/* Rest of capability flags */
#define PCI_AGP_STATUS		4	/* Status register */
#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
#define PCI_AGP_COMMAND		8	/* Control register */
#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
#define PCI_AGP_SIZEOF		12

/* Slot Identification */

#define PCI_SID_ESR		2	/* Expansion Slot Register */
#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */

/* Message Signalled Interrupts registers */

#define PCI_MSI_FLAGS		2	/* Various flags */
#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
#define PCI_MSI_RFU		3	/* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */











#define PCI_FUNC(devfn)           ((devfn) & 0x07)
struct pci_support_device {
	unsigned short	vendor, dev_id;
	const char		*name;
};

struct pci_config_data
{
	WORD	 vendorID ;
	WORD	 deviceID ;
	WORD	 command_reg ;
	WORD	 status_reg ;
	BYTE	 revisionID ;
	BYTE	 progIF ;
	BYTE	 subclass ;
	BYTE	 classcode ;
	BYTE	 cacheline_size ;
	BYTE	 latency ;
	BYTE	 header_type ;
	BYTE	 BIST ;
	union{
		struct{
			DWORD base_address0 ;
			DWORD base_address1 ;
			DWORD base_address2 ;
			DWORD base_address3 ;
			DWORD base_address4 ;
			DWORD base_address5 ;
			DWORD CardBus_CIS ;
			WORD  subsystem_vendorID ;
			WORD  subsystem_deviceID ;
			DWORD expansion_ROM ;
			BYTE  cap_ptr ;
			BYTE  reserved1[3] ;
			DWORD reserved2[1] ;
			BYTE  interrupt_line ;
			BYTE  interrupt_pin ;
			BYTE  min_grant ;
			BYTE  max_latency ;
			DWORD device_specific[48] ;
		} nonbridge;
		struct{
			DWORD base_address0 ;
			DWORD base_address1 ;
			BYTE  primary_bus ;
			BYTE  secondary_bus ;
			BYTE  subordinate_bus ;
			BYTE  secondary_latency ;
			BYTE  IO_base_low ;
			BYTE  IO_limit_low ;
			WORD  secondary_status ;
			WORD  memory_base_low ;
			WORD  memory_limit_low ;
			WORD  prefetch_base_low ;
			WORD  prefetch_limit_low ;
			DWORD prefetch_base_high ;
			DWORD prefetch_limit_high ;
			WORD  IO_base_high ;
			WORD  IO_limit_high ;
			DWORD reserved2[1] ;
			DWORD expansion_ROM ;
			BYTE  interrupt_line ;
			BYTE  interrupt_pin ;
			WORD  bridge_control ;
			DWORD device_specific[48] ;
		} bridge;
		struct{
			DWORD ExCa_base ;
			BYTE  cap_ptr ;
			BYTE  reserved05 ;
			WORD  secondary_status ;
			BYTE  PCI_bus ;
			BYTE  CardBus_bus ;
			BYTE  subordinate_bus ;
			BYTE  latency_timer ;
			DWORD memory_base0 ;
			DWORD memory_limit0 ;
			DWORD memory_base1 ;
			DWORD memory_limit1 ;
			WORD  IObase_0low ;
			WORD  IObase_0high ;
			WORD  IOlimit_0low ;
			WORD  IOlimit_0high ;
			WORD  IObase_1low ;
			WORD  IObase_1high ;
			WORD  IOlimit_1low ;
			WORD  IOlimit_1high ;
			BYTE  interrupt_line ;
			BYTE  interrupt_pin ;
			WORD  bridge_control ;
			WORD  subsystem_vendorID ;
			WORD  subsystem_deviceID ;
			DWORD legacy_baseaddr ;
			DWORD cardbus_reserved[14] ;
			DWORD vendor_specific[32] ;
		} cardbus;
	}U;
};

struct pci_device {
	int	devfn;
	int	bus;
	int irq;
	unsigned short ioaddr;
	unsigned long  membase;
        unsigned short vendor,device;
	const char *name;
	union {
		unsigned char raw[1];
		struct pci_config_data config_data;
	}U;
	struct pci_device *next;
};


extern void init_pci_bus(void);
extern void dump_pci_device(void);
extern int pcibios_read_config_byte(unsigned long  bus, unsigned long  device_fn,
                               unsigned long  where, unsigned char *value);

extern struct pci_device *lookup_pci_device(unsigned short vendor,unsigned short device);
extern int pcibios_read_config_word (unsigned long  bus,
    unsigned long  device_fn, unsigned long  where, unsigned short *value);

extern int pcibios_read_config_dword (unsigned long  bus, unsigned long  device_fn,
                                 unsigned long  where, unsigned long  *value);

extern int pcibios_write_config_byte (unsigned long  bus, unsigned long  device_fn,
                                 unsigned long  where, unsigned char value);

extern int pcibios_write_config_word (unsigned long  bus, unsigned long  device_fn,
                                 unsigned long  where, unsigned short value);

extern int pcibios_write_config_dword (unsigned long  bus, unsigned long  device_fn,
                                 unsigned long  where, unsigned long value);
#endif