📄 unpack.lst
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TMS320C54x COFF Assembler Beta Version 1.16 Mon Sep 23 13:59:00 1996
Copyright (c) 1996 Texas Instruments Incorporated
unpack.asm PAGE 1
1 *********************************************************************************
2 * (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 *
3 *********************************************************************************
4 * *
5 * MODULE NAME: unpack.asm *
6 * *
7 * AUTHORS: Simon Lau and Nathan Baltz *
8 * *
9 * DESCRIPTION: PHASE THREE & FOUR Unpacking to 2N Outputs *
10 * This function is called from the main module of the 'C54x Real *
11 * FFT code. It first computes four intermediate sequences (RP, *
12 * RM, IP, IM) from the resulting complex sequence at the end of *
13 * the previous phase. Next, it uses the four intermediate *
14 * sequences to form the FFT of the original 2N-point real input. *
15 * Again, the outputs are divided by 2 to prevent overflow. *
16 * *
17 * REGISTER USAGE: AR0 index of twiddle tables *
18 * (PHASE THREE) AR2 pointer to R[k], I[k], RP[k], IP[k] *
19 * AR3 pointer to R[N-k], I[N-k], RP[N-k], IP[N-k] *
20 * AR6 pointer to RM[k], IM[k] *
21 * AR7 pointer to RM[N-k], IM[N-k] *
22 * *
23 * REGISTER USAGE: AR0 index of twiddle tables *
24 * (PHASE FOUR) AR2 pointer to RP[k], IP[k], AR[k], AI[k], AR[0] *
25 * AR3 pointer to RM[k], IM[k], AR[2N-k], AI[2N-k] *
26 * AR4 pointer to cos(k*pi/N), AI[0] *
27 * AR5 pointer to sin(k*pi/N), AR[N], AI[N] *
28 * *
29 * DATE: 7-16-1996 *
30 * *
31 *********************************************************************************
32
33 .mmregs
34 .include "fft_size.inc"
35 .def unpack
36 .ref fft_data, sine, cosine
37
38
39 000000 .text
40
41 000000 unpack:
42
43 ; Compute intermediate values RP, RM, IP, IM
44
45 .asg AR2,XP_k
46 .asg AR3,XP_Nminusk
47 .asg AR6,XM_k
48 .asg AR7,XM_Nminusk
49
50 000000 7712 STM #fft_data+2,XP_k ; AR2 -> R[k] (temp RP[k])
000001 0002!
51 000002 7713 STM #fft_data+2*K_FFT_SIZE-2,XP_Nminusk ; AR3 -> R[N-k] (temp RP[N-k])
000003 000E!
52 000004 7717 STM #fft_data+2*K_FFT_SIZE+3,XM_Nminusk ; AR7 -> temp RM[N-k]
000005 0013!
TMS320C54x COFF Assembler Beta Version 1.16 Mon Sep 23 13:59:00 1996
Copyright (c) 1996 Texas Instruments Incorporated
unpack.asm PAGE 2
53 000006 7716 STM #fft_data+4*K_FFT_SIZE-1,XM_k ; AR6 -> temp RM[k]
000007 001F!
54 000008 771A STM #-2+K_FFT_SIZE/2,BRC
000009 0002
55 00000a F272 RPTBD phase3end-1
00000b 001B'
56 00000c 7710 STM #3,AR0
00000d 0003
57
58 00000e A001 ADD *XP_k,*XP_Nminusk,A ; A := R[k]+R[N-k] = 2*RP[k]
59 00000f A301 SUB *XP_k,*XP_Nminusk,B ; B := R[k]-R[N-k] = 2*RM[k]
60 000010 8692 STH A,ASM,*XP_k+ ; store RP[k] at AR[k]
61 000011 8693 STH A,ASM,*XP_Nminusk+ ; store RP[N-k]=RP[k] at AR[N-k]
62 000012 878E STH B,ASM,*XM_k- ; store RM[k] at AI[2N-k]
63 000013 F784 NEG B ; B := R[N-k]-R[k] = 2*RM[N-k]
64 000014 878F STH B,ASM,*XM_Nminusk- ; store RM[N-k] at AI[N+k]
65
66 000015 A001 ADD *XP_k,*XP_Nminusk,A ; A := I[k]+I[N-k] = 2*IP[k]
67 000016 A301 SUB *XP_k,*XP_Nminusk,B ; B := I[k]-I[N-k] = 2*IM[k]
68 000017 8692 STH A,ASM,*XP_k+ ; store IP[k] at AI[k]
69 000018 86AB STH A,ASM,*XP_Nminusk-0 ; store IP[N-k]=IP[k] at AI[N-k]
70 000019 878E STH B,ASM,*XM_k- ; store IM[k] at AR[2N-k]
71 00001a F784 NEG B ; B := I[N-k]-I[k] = 2*IM[N-k]
72 00001b 87B7 STH B,ASM,*XM_Nminusk+0 ; store IM[N-k] at AR[N+k]
73
74 00001c phase3end:
75 00001c 768E ST #0,*XM_k- ; RM[N/2]=0
00001d 0000
76 00001e 7686 ST #0,*XM_k ; IM[N/2]=0
00001f 0000
77
78
79 ; Compute AR[0], AI[0], AR[N], AI[N]
80
81 .asg AR2,AX_k
82 .asg AR4,IP_0
83 .asg AR5,AX_N
84
85 000020 7712 STM #fft_data,AX_k ; AR2 -> AR[0] (temp RP[0])
000021 0000!
86 000022 7714 STM #fft_data+1,IP_0 ; AR4 -> AI[0] (temp IP[0])
000023 0001!
87 000024 7715 STM #fft_data+2*K_FFT_SIZE+1,AX_N ; AR5 -> AI[N]
000025 0011!
88 000026 A002 ADD *AX_k,*IP_0,A ; A := RP[0]+IP[0]
89 000027 A302 SUB *AX_k,*IP_0,B ; B := RP[0]-IP[0]
90 000028 8692 STH A,ASM,*AX_k+ ; AR[0] = (RP[0]+IP[0])/2
91 000029 7682 ST #0,*AX_k ; AI[0] = 0
00002a 0000
92 00002b E587 MVDD *AX_k+,*AX_N- ; AI[N] = 0
93 00002c 8785 STH B,ASM,*AX_N ; AR[N] = (RP[0]-IP[0])/2
94
95
96 ; Compute final output values AR[k], AI[k]
97
TMS320C54x COFF Assembler Beta Version 1.16 Mon Sep 23 13:59:00 1996
Copyright (c) 1996 Texas Instruments Incorporated
unpack.asm PAGE 3
98 .asg AR3,AX_2Nminusk
99 .asg AR4,COS
100 .asg AR5,SIN
101
102 00002d 7713 STM #fft_data+4*K_FFT_SIZE-1,AX_2Nminusk ; AR3 -> AI[2N-1] (temp RM[1])
00002e 001F!
103 00002f 7714 STM #cosine+512/K_FFT_SIZE,COS ; AR4 -> cos(k*pi/N)
000030 0040!
104 000031 7715 STM #sine+512/K_FFT_SIZE,SIN ; AR5 -> sin(k*pi/N)
000032 0040!
105 000033 771A STM #K_FFT_SIZE-2,BRC
000034 0006
106 000035 F272 RPTBD phase4end-1
000036 0043'
107 000037 7710 STM #512/K_FFT_SIZE,AR0 ; index of twiddle tables
000038 0040
108
109 000039 4492 LD *AX_k+,16,A ; A := RP[k] || AR2->IP[k]
110 00003a B420 MACR *COS,*AX_k,A ; A := A+cos(k*pi/N)*IP[k]
111 00003b BC35 MASR *SIN,*AX_2Nminusk-,A ; A := A-sin(k*pi/N)*RM[k]
112 ; || AR3->IM[k]
113 00003c 4593 LD *AX_2Nminusk+,16,B ; B := IM[k] || AR3->RM[k]
114 00003d BFF4 MASR *SIN+0%,*AX_k-,B ; B := B-sin(k*pi/N)*IP[k]
115 ; || AR2->RP[k]
116 00003e BFE1 MASR *COS+0%,*AX_2Nminusk,B ; B := B-cos(k*pi/N)*RM[k]
117 00003f 8692 STH A,ASM,*AX_k+ ; AR[k] = A/2
118 000040 8792 STH B,ASM,*AX_k+ ; AI[k] = B/2
119 000041 F784 NEG B ; B := -B
120 000042 878B STH B,ASM,*AX_2Nminusk- ; AI[2N-k] = -AI[k] = B/2
121 000043 868B STH A,ASM,*AX_2Nminusk- ; AR[2N-k] = AR[k] = A/2
122
123 000044 phase4end:
124 000044 FC00 RET ; return to Real FFT main module
125
126 .end
No Errors, No Warnings
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