xllp_gpio.c

pxa27x library for windows ce 5.0

/******************************************************************************
**
**  COPYRIGHT (C) 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
**  only, is subject to change without notice, and should not be consXLLP_TRUEd as
**  a commitment by Intel Corporation. Intel Corporation assumes no
**  responsibility or liability for any errors or inaccuracies that may appear
**  in this document or any software that may be provided in association with
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:   xllp_gpio.c
**
**  PURPOSE:    contains XLLP GPIO primitives.
**  
******************************************************************************/


#include "xllp_gpio.h"
#include "xllp_serialization.h"

/**
 * General-purpose I/O access routines 
 * Registers:
 *	GPLR_0,1,2,3:	line-level registers
 *	GPDR_0,1,2,3:	data-direction registers
 *	GPSR_0,1,2,3:	set registers
 *	GPCR_0,1,2,3:	clear registers
 *	GRER_0,1,2,3:	rising-edge detect registers
 *	GFER_0,1,2,3:	falling-edge detect registers
 *	GEDR_0,1,2,3:	edge-detect status register
 *	GAFR0_L: alternate function select registers
 *  GAFR0_U: alternate function select registers
 *	GAFR1_L: alternate function select registers
 *  GAFR1_U: alternate function select registers
 *	GAFR2_L: alternate function select registers
 *  GAFR2_U: alternate function select registers
 *	GAFR3_L: alternate function select registers
 *  GAFR3_U: alternate function select registers
 */


/**
 * Levels
 */
XLLP_UINT32_T XllpGpioGetState  
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin)
/**
 * Read GPIO pin level from the register specified by aGpioPin
 * GPLR Read Only Register
 */
	{
	XLLP_UINT32_T aGpioPinMask;

	aGpioPinMask = 0x1 << (aGpioPin & 0x1F);

	if(aGpioPin > 95)
		return (pGPIO->GPLR3 & aGpioPinMask);
	else if(aGpioPin > 63) 
		return (pGPIO->GPLR2 & aGpioPinMask);
	else if(aGpioPin > 31) 
		return (pGPIO->GPLR1 & aGpioPinMask);
	else return (pGPIO->GPLR0 & aGpioPinMask);
	}

/**
 * Data direction
 */

/**
 * Read GPIO pin direction DDR
 * return 0=input, 1=output
 */
XLLP_UINT32_T XllpGpioGetDirection 
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin)
    {
	XLLP_UINT32_T aGpioPinMask;

	aGpioPinMask = 0x1 << (aGpioPin & 0x1F);

	if(aGpioPin > 95)
		return (pGPIO->GPDR3 & aGpioPinMask);
	else if(aGpioPin > 63) 
		return (pGPIO->GPDR2 & aGpioPinMask);
	else if(aGpioPin > 31) 
		return (pGPIO->GPDR1 & aGpioPinMask);
	else return (pGPIO->GPDR0 & aGpioPinMask);
    }

/**
 * Modify GP DDR For Input Direction
 */
/*
 * aGpioPinArray[]=array of GPIO pins
 * aGpioPinArray[0] = size of array
 */
void XllpGpioSetDirectionIn 
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[])
    {
	XLLP_UINT32_T LockID;
	XLLP_UINT32_T aGpioPinMask;
	XLLP_UINT32_T aSizeArray;
	XLLP_UINT32_T aMask0, aMask1, aMask2, aMask3;
	XLLP_BOOL_T aSet0, aSet1, aSet2, aSet3;
	XLLP_UINT32_T i;

	//determine size of array
	aSizeArray = aGpioPinArray[0];
	aMask0=aMask1=aMask2=aMask3=0;
	aSet0=aSet1=aSet2=aSet3=XLLP_FALSE;

	for(i=1; i<=aSizeArray; i++)
	{
		aGpioPinMask = 0x1u << (aGpioPinArray[i] & 0x1F);
		if(aGpioPinArray[i] > 95)
		{
			aMask3 |= aGpioPinMask;
			aSet3=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 63)
		{
			aMask2 |= aGpioPinMask;
			aSet2=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 31)
		{ 
			aMask1 |= aGpioPinMask;
			aSet1=XLLP_TRUE;
		}
		else
		{
			aMask0 |= aGpioPinMask;
			aSet0=XLLP_TRUE;
		}
			
	}
	
	if(aSet3)
	{
		LockID = XllpLock(GPDR3);
		pGPIO->GPDR3=((pGPIO->GPDR3&~aMask3)&~XLLP_GPIO_PIN_RESERVED_BITS);
		XllpUnlock(LockID);
	}
	if(aSet2)
	{
		LockID = XllpLock(GPDR2);
		pGPIO->GPDR2=((pGPIO->GPDR2)&~aMask2);
		XllpUnlock(LockID);
	}
	if(aSet1)
	{
		LockID = XllpLock(GPDR1);
		pGPIO->GPDR1=((pGPIO->GPDR1)&~aMask1);
		XllpUnlock(LockID);
	}
	if(aSet0)
	{
		LockID = XllpLock(GPDR0);
		pGPIO->GPDR0=((pGPIO->GPDR0)&~aMask0);
		XllpUnlock(LockID);
	}
    }

/**
 * Modify GP DDR For Output Direction
 */
/*
 * aGpioPinArray[]=array of GPIO pins
 * aGpioPinArray[0] = size of array
 */
void XllpGpioSetDirectionOut 
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[])
    {
	XLLP_UINT32_T LockID;
	XLLP_UINT32_T aGpioPinMask;
	XLLP_UINT32_T aSizeArray;
	XLLP_UINT32_T aMask0, aMask1, aMask2, aMask3;
	XLLP_BOOL_T aSet0, aSet1, aSet2, aSet3;
	XLLP_UINT32_T i;

	//determine size of array
	aSizeArray = aGpioPinArray[0];
	aMask0=aMask1=aMask2=aMask3=0;
	aSet0=aSet1=aSet2=aSet3=XLLP_FALSE;
	
	for(i=1; i<=aSizeArray; i++)
	{
		aGpioPinMask = 0x1u << (aGpioPinArray[i] & 0x1F);
		if(aGpioPinArray[i] > 95)
		{
			aMask3 |= aGpioPinMask;
			aSet3=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 63)
		{
			aMask2 |= aGpioPinMask;
			aSet2=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 31)
		{
			aMask1 |= aGpioPinMask;
			aSet1=XLLP_TRUE;
		}
		else
		{
			aMask0 |= aGpioPinMask;
			aSet0=XLLP_TRUE;
		}
	}
	if(aSet3)
	{
		LockID = XllpLock(GPDR3);
		pGPIO->GPDR3=((pGPIO->GPDR3| aMask3)&~XLLP_GPIO_PIN_RESERVED_BITS);
		XllpUnlock(LockID);
	}
	if(aSet2)
	{
		LockID = XllpLock(GPDR2);
		pGPIO->GPDR2=((pGPIO->GPDR2)| aMask2);
		XllpUnlock(LockID);
	}
	if(aSet1)
	{
		LockID = XllpLock(GPDR1);
		pGPIO->GPDR1=((pGPIO->GPDR1)| aMask1);
		XllpUnlock(LockID);
	}
	if(aSet0)
	{
		LockID = XllpLock(GPDR0);
		pGPIO->GPDR0=((pGPIO->GPDR0)| aMask0);
		XllpUnlock(LockID);
	}
    }

/*
 * aGpioPinArray[]=array of GPIO pins
 * aGpioPinArray[0] = size of array
 * Set GPIO output pin to level'1'
 * Write-0 ignored
 */
void XllpGpioSetOutputState1 
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[])
	{
	XLLP_UINT32_T aGpioPinMask;
	XLLP_UINT32_T aSizeArray;
	XLLP_UINT32_T aMask0, aMask1, aMask2, aMask3;
	XLLP_BOOL_T aSet0, aSet1, aSet2, aSet3;
	XLLP_UINT32_T i;

	//determine size of array
	aSizeArray = aGpioPinArray[0];
	aMask0=aMask1=aMask2=aMask3=0;
	aSet0=aSet1=aSet2=aSet3=XLLP_FALSE;

	for(i=1; i<=aSizeArray; i++)
	{
		aGpioPinMask = 0x1u << (aGpioPinArray[i] & 0x1F);
		if(aGpioPinArray[i] > 95)
		{
			aMask3 |= aGpioPinMask;
			aSet3=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 63)
		{
			aMask2 |= aGpioPinMask;
			aSet2=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 31)
		{
			aMask1 |= aGpioPinMask;
			aSet1=XLLP_TRUE;
		}
		else
		{
			aMask0 |= aGpioPinMask;
			aSet0=XLLP_TRUE;
		}
	}
	if(aSet3)
		pGPIO->GPSR3=aMask3;
	if(aSet2)
		pGPIO->GPSR2=aMask2;
	if(aSet1)
		pGPIO->GPSR1=aMask1;
	if(aSet0)
		pGPIO->GPSR0=aMask0;
	}

/*
 * aGpioPinArray[]=array of GPIO pins
 * aGpioPinArray[0] = size of array
 * Set GPIO output pin to level'0'
 * Write-0 ignored
 */
void XllpGpioSetOutput0 
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[])
	{
	XLLP_UINT32_T aGpioPinMask;
	XLLP_UINT32_T aSizeArray;
	XLLP_UINT32_T aMask0, aMask1, aMask2, aMask3;
	XLLP_BOOL_T aSet0, aSet1, aSet2, aSet3;
	XLLP_UINT32_T i;

	//determine size of array
	aSizeArray = aGpioPinArray[0];
	aMask0=aMask1=aMask2=aMask3=0;
	aSet0=aSet1=aSet2=aSet3=XLLP_FALSE;

	for(i=1; i<=aSizeArray; i++)
	{
		aGpioPinMask = 0x1u << (aGpioPinArray[i] & 0x1F);
		if(aGpioPinArray[i] > 95)
		{
			aMask3 |= aGpioPinMask;
			aSet3=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 63)
		{
			aMask2 |= aGpioPinMask;
			aSet2=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 31)
		{
			aMask1 |= aGpioPinMask;
			aSet1=XLLP_TRUE;
		}
		else
		{
			aMask0 |= aGpioPinMask;
			aSet0=XLLP_TRUE;
		}
	}
	if(aSet3)
		pGPIO->GPCR3=aMask3;
	if(aSet2)
		pGPIO->GPCR2=aMask2;
	if(aSet1)
		pGPIO->GPCR1=aMask1;
	if(aSet0)
		pGPIO->GPCR0=aMask0;
	}

/**
 * Read GRER for a Gpio pin specified by aGpioPin 
 */
XLLP_UINT32_T XllpGpioGetRisingDetectEnable 
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin)
/**
 * Read GRER: 
 * return 1=edge detect enable, 0=edge detect disable
 */
	{
	
	XLLP_UINT32_T aGpioPinMask;

	aGpioPinMask = 0x1 << (aGpioPin & 0x1F);

	if(aGpioPin > 95)
		return (pGPIO->GRER3& aGpioPinMask);
	else if(aGpioPin > 63) 
		return (pGPIO->GRER2 & aGpioPinMask);
	else if(aGpioPin > 31) 
		return (pGPIO->GRER1 & aGpioPinMask);
	else return (pGPIO->GRER0 & aGpioPinMask);
	}

/*
 * aGpioPinArray[]=array of GPIO pins
 * aGpioPinArray[0] = size of array
 * Disable Rising Edge Detect
 */
void XllpGpioSetRisingDetectDisable 
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[])
	{
	XLLP_UINT32_T LockID;
	XLLP_UINT32_T aGpioPinMask;
	XLLP_UINT32_T aSizeArray;
	XLLP_UINT32_T aMask0, aMask1, aMask2, aMask3;
	XLLP_BOOL_T aSet0, aSet1, aSet2, aSet3;
	XLLP_UINT32_T i;

	//determine size of array
	aSizeArray = aGpioPinArray[0];
	aMask0=aMask1=aMask2=aMask3=0;
	aSet0=aSet1=aSet2=aSet3=XLLP_FALSE;

	for(i=1; i<=aSizeArray; i++)
	{
		aGpioPinMask = 0x1u << (aGpioPinArray[i] & 0x1F);
		if(aGpioPinArray[i] > 95)
		{
			aMask3 |= aGpioPinMask;
			aSet3=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 63)
		{
			aMask2 |= aGpioPinMask;
			aSet2=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 31)
		{
			aMask1 |= aGpioPinMask;
			aSet1=XLLP_TRUE;
		}
		else
		{
			aMask0 |= aGpioPinMask;
			aSet0=XLLP_TRUE;
		}
	}
	if(aSet3)
	{
		LockID = XllpLock(GRER3);
		pGPIO->GRER3=((pGPIO->GRER3&~aMask3)&~XLLP_GPIO_PIN_RESERVED_BITS);
		XllpUnlock(LockID);
	}
	if(aSet2)
	{
		LockID = XllpLock(GRER2);
		pGPIO->GRER2=((pGPIO->GRER2)&~aMask2);
		XllpUnlock(LockID);
	}
	if(aSet1)
	{
		LockID = XllpLock(GRER1);
		pGPIO->GRER1=((pGPIO->GRER1)&~aMask1);
		XllpUnlock(LockID);
	}
	if(aSet0)
	{
		LockID = XllpLock(GRER0);
		pGPIO->GRER0=((pGPIO->GRER0)&~aMask0);
		XllpUnlock(LockID);
	}
	}

/*
 * aGpioPinArray[]=array of GPIO pins
 * aGpioPinArray[0] = size of array
 * Enable Rising Edge Detect
 */
void XllpGpioSetRisingDetectEnable 
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[])
	{
	XLLP_UINT32_T LockID;
	XLLP_UINT32_T aGpioPinMask;
	XLLP_UINT32_T aSizeArray;
	XLLP_UINT32_T aMask0, aMask1, aMask2, aMask3;
	XLLP_BOOL_T aSet0, aSet1, aSet2, aSet3;
	XLLP_UINT32_T i;

	//determine size of array
	aSizeArray = aGpioPinArray[0];
	aMask0=aMask1=aMask2=aMask3=0;
	aSet0=aSet1=aSet2=aSet3=XLLP_FALSE;

	for(i=1; i<=aSizeArray; i++)
	{
		aGpioPinMask = 0x1u << (aGpioPinArray[i] & 0x1F);
		if(aGpioPinArray[i] > 95)
		{
			aMask3 |= aGpioPinMask;
			aSet3=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 63)
		{
			aMask2 |= aGpioPinMask;
			aSet2=XLLP_TRUE;
		}
		else if(aGpioPinArray[i] > 31)
		{
			aMask1 |= aGpioPinMask;
			aSet1=XLLP_TRUE;
		}
		else
		{
			aMask0 |= aGpioPinMask;
			aSet0=XLLP_TRUE;
		}
	}
	if(aSet3)
	{
		LockID = XllpLock(GRER3);
		pGPIO->GRER3=((pGPIO->GRER3|aMask3)&~XLLP_GPIO_PIN_RESERVED_BITS);
		XllpUnlock(LockID);
	}
	if(aSet2)
	{
		LockID = XllpLock(GRER2);
		pGPIO->GRER2=((pGPIO->GRER2)|aMask2);
		XllpUnlock(LockID);
	}
	if(aSet1)
	{
		LockID = XllpLock(GRER1);
		pGPIO->GRER1=((pGPIO->GRER1)|aMask1);
		XllpUnlock(LockID);
	}
	if(aSet0)
	{
		LockID = XllpLock(GRER0);
		pGPIO->GRER0=((pGPIO->GRER0)|aMask0);
		XllpUnlock(LockID);
	}
	}

/**
 * Read GFER for a Gpio pin specified by aGpioPin 
 */
XLLP_UINT32_T XllpGpioGetFallingDetectEnable 
     (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin)
/**
 * Read GFER: 
 * return 1=falling edge detect enable, 0=falling edge detect disable