tg3.h

linux下从网卡远程启动

#define GRCMBOX_SNDNIC_PROD_IDX_10	0x000059d0 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_11	0x000059d8 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_12	0x000059e0 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_13	0x000059e8 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_14	0x000059f0 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_15	0x000059f8 /* 64-bit */
#define GRCMBOX_HIGH_PRIO_EV_VECTOR	0x00005a00
#define GRCMBOX_HIGH_PRIO_EV_MASK	0x00005a04
#define GRCMBOX_LOW_PRIO_EV_VEC		0x00005a08
#define GRCMBOX_LOW_PRIO_EV_MASK	0x00005a0c
/* 0x5a10 --> 0x5c00 */

/* Flow Through queues */
#define FTQ_RESET			0x00005c00
/* 0x5c04 --> 0x5c10 unused */
#define FTQ_DMA_NORM_READ_CTL		0x00005c10
#define FTQ_DMA_NORM_READ_FULL_CNT	0x00005c14
#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ	0x00005c18
#define FTQ_DMA_NORM_READ_WRITE_PEEK	0x00005c1c
#define FTQ_DMA_HIGH_READ_CTL		0x00005c20
#define FTQ_DMA_HIGH_READ_FULL_CNT	0x00005c24
#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ	0x00005c28
#define FTQ_DMA_HIGH_READ_WRITE_PEEK	0x00005c2c
#define FTQ_DMA_COMP_DISC_CTL		0x00005c30
#define FTQ_DMA_COMP_DISC_FULL_CNT	0x00005c34
#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ	0x00005c38
#define FTQ_DMA_COMP_DISC_WRITE_PEEK	0x00005c3c
#define FTQ_SEND_BD_COMP_CTL		0x00005c40
#define FTQ_SEND_BD_COMP_FULL_CNT	0x00005c44
#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ	0x00005c48
#define FTQ_SEND_BD_COMP_WRITE_PEEK	0x00005c4c
#define FTQ_SEND_DATA_INIT_CTL		0x00005c50
#define FTQ_SEND_DATA_INIT_FULL_CNT	0x00005c54
#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ	0x00005c58
#define FTQ_SEND_DATA_INIT_WRITE_PEEK	0x00005c5c
#define FTQ_DMA_NORM_WRITE_CTL		0x00005c60
#define FTQ_DMA_NORM_WRITE_FULL_CNT	0x00005c64
#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ	0x00005c68
#define FTQ_DMA_NORM_WRITE_WRITE_PEEK	0x00005c6c
#define FTQ_DMA_HIGH_WRITE_CTL		0x00005c70
#define FTQ_DMA_HIGH_WRITE_FULL_CNT	0x00005c74
#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ	0x00005c78
#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK	0x00005c7c
#define FTQ_SWTYPE1_CTL			0x00005c80
#define FTQ_SWTYPE1_FULL_CNT		0x00005c84
#define FTQ_SWTYPE1_FIFO_ENQDEQ		0x00005c88
#define FTQ_SWTYPE1_WRITE_PEEK		0x00005c8c
#define FTQ_SEND_DATA_COMP_CTL		0x00005c90
#define FTQ_SEND_DATA_COMP_FULL_CNT	0x00005c94
#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ	0x00005c98
#define FTQ_SEND_DATA_COMP_WRITE_PEEK	0x00005c9c
#define FTQ_HOST_COAL_CTL		0x00005ca0
#define FTQ_HOST_COAL_FULL_CNT		0x00005ca4
#define FTQ_HOST_COAL_FIFO_ENQDEQ	0x00005ca8
#define FTQ_HOST_COAL_WRITE_PEEK	0x00005cac
#define FTQ_MAC_TX_CTL			0x00005cb0
#define FTQ_MAC_TX_FULL_CNT		0x00005cb4
#define FTQ_MAC_TX_FIFO_ENQDEQ		0x00005cb8
#define FTQ_MAC_TX_WRITE_PEEK		0x00005cbc
#define FTQ_MB_FREE_CTL			0x00005cc0
#define FTQ_MB_FREE_FULL_CNT		0x00005cc4
#define FTQ_MB_FREE_FIFO_ENQDEQ		0x00005cc8
#define FTQ_MB_FREE_WRITE_PEEK		0x00005ccc
#define FTQ_RCVBD_COMP_CTL		0x00005cd0
#define FTQ_RCVBD_COMP_FULL_CNT		0x00005cd4
#define FTQ_RCVBD_COMP_FIFO_ENQDEQ	0x00005cd8
#define FTQ_RCVBD_COMP_WRITE_PEEK	0x00005cdc
#define FTQ_RCVLST_PLMT_CTL		0x00005ce0
#define FTQ_RCVLST_PLMT_FULL_CNT	0x00005ce4
#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ	0x00005ce8
#define FTQ_RCVLST_PLMT_WRITE_PEEK	0x00005cec
#define FTQ_RCVDATA_INI_CTL		0x00005cf0
#define FTQ_RCVDATA_INI_FULL_CNT	0x00005cf4
#define FTQ_RCVDATA_INI_FIFO_ENQDEQ	0x00005cf8
#define FTQ_RCVDATA_INI_WRITE_PEEK	0x00005cfc
#define FTQ_RCVDATA_COMP_CTL		0x00005d00
#define FTQ_RCVDATA_COMP_FULL_CNT	0x00005d04
#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ	0x00005d08
#define FTQ_RCVDATA_COMP_WRITE_PEEK	0x00005d0c
#define FTQ_SWTYPE2_CTL			0x00005d10
#define FTQ_SWTYPE2_FULL_CNT		0x00005d14
#define FTQ_SWTYPE2_FIFO_ENQDEQ		0x00005d18
#define FTQ_SWTYPE2_WRITE_PEEK		0x00005d1c
/* 0x5d20 --> 0x6000 unused */

/* Message signaled interrupt registers */
#define MSGINT_MODE			0x00006000
#define  MSGINT_MODE_RESET		 0x00000001
#define  MSGINT_MODE_ENABLE		 0x00000002
#define MSGINT_STATUS			0x00006004
#define MSGINT_FIFO			0x00006008
/* 0x600c --> 0x6400 unused */

/* DMA completion registers */
#define DMAC_MODE			0x00006400
#define  DMAC_MODE_RESET		 0x00000001
#define  DMAC_MODE_ENABLE		 0x00000002
/* 0x6404 --> 0x6800 unused */

/* GRC registers */
#define GRC_MODE			0x00006800
#define  GRC_MODE_UPD_ON_COAL		0x00000001
#define  GRC_MODE_BSWAP_NONFRM_DATA	0x00000002
#define  GRC_MODE_WSWAP_NONFRM_DATA	0x00000004
#define  GRC_MODE_BSWAP_DATA		0x00000010
#define  GRC_MODE_WSWAP_DATA		0x00000020
#define  GRC_MODE_SPLITHDR		0x00000100
#define  GRC_MODE_NOFRM_CRACKING	0x00000200
#define  GRC_MODE_INCL_CRC		0x00000400
#define  GRC_MODE_ALLOW_BAD_FRMS	0x00000800
#define  GRC_MODE_NOIRQ_ON_SENDS	0x00002000
#define  GRC_MODE_NOIRQ_ON_RCV		0x00004000
#define  GRC_MODE_FORCE_PCI32BIT	0x00008000
#define  GRC_MODE_HOST_STACKUP		0x00010000
#define  GRC_MODE_HOST_SENDBDS		0x00020000
#define  GRC_MODE_NO_TX_PHDR_CSUM	0x00100000
#define  GRC_MODE_NO_RX_PHDR_CSUM	0x00800000
#define  GRC_MODE_IRQ_ON_TX_CPU_ATTN	0x01000000
#define  GRC_MODE_IRQ_ON_RX_CPU_ATTN	0x02000000
#define  GRC_MODE_IRQ_ON_MAC_ATTN	0x04000000
#define  GRC_MODE_IRQ_ON_DMA_ATTN	0x08000000
#define  GRC_MODE_IRQ_ON_FLOW_ATTN	0x10000000
#define  GRC_MODE_4X_NIC_SEND_RINGS	0x20000000
#define  GRC_MODE_MCAST_FRM_ENABLE	0x40000000
#define GRC_MISC_CFG			0x00006804
#define  GRC_MISC_CFG_CORECLK_RESET	0x00000001
#define  GRC_MISC_CFG_PRESCALAR_MASK	0x000000fe
#define  GRC_MISC_CFG_PRESCALAR_SHIFT	1
#define  GRC_MISC_CFG_BOARD_ID_MASK	0x0001e000
#define  GRC_MISC_CFG_BOARD_ID_5700	0x0001e000
#define  GRC_MISC_CFG_BOARD_ID_5701	0x00000000
#define  GRC_MISC_CFG_BOARD_ID_5702FE	0x00004000
#define  GRC_MISC_CFG_BOARD_ID_5703	0x00000000
#define  GRC_MISC_CFG_BOARD_ID_5703S	0x00002000
#define  GRC_MISC_CFG_BOARD_ID_5704	0x00000000
#define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
#define  GRC_MISC_CFG_BOARD_ID_5704_A2	0x00008000
#define  GRC_MISC_CFG_BOARD_ID_5788	0x00010000
#define  GRC_MISC_CFG_BOARD_ID_5788M	0x00018000
#define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
#define  GRC_MISC_CFG_KEEP_GPHY_POWER	0x04000000
#define GRC_LOCAL_CTRL			0x00006808
#define  GRC_LCLCTRL_INT_ACTIVE		0x00000001
#define  GRC_LCLCTRL_CLEARINT		0x00000002
#define  GRC_LCLCTRL_SETINT		0x00000004
#define  GRC_LCLCTRL_INT_ON_ATTN	0x00000008
#define  GRC_LCLCTRL_GPIO_INPUT0	0x00000100
#define  GRC_LCLCTRL_GPIO_INPUT1	0x00000200
#define  GRC_LCLCTRL_GPIO_INPUT2	0x00000400
#define  GRC_LCLCTRL_GPIO_OE0		0x00000800
#define  GRC_LCLCTRL_GPIO_OE1		0x00001000
#define  GRC_LCLCTRL_GPIO_OE2		0x00002000
#define  GRC_LCLCTRL_GPIO_OUTPUT0	0x00004000
#define  GRC_LCLCTRL_GPIO_OUTPUT1	0x00008000
#define  GRC_LCLCTRL_GPIO_OUTPUT2	0x00010000
#define  GRC_LCLCTRL_EXTMEM_ENABLE	0x00020000
#define  GRC_LCLCTRL_MEMSZ_MASK		0x001c0000
#define  GRC_LCLCTRL_MEMSZ_256K		0x00000000
#define  GRC_LCLCTRL_MEMSZ_512K		0x00040000
#define  GRC_LCLCTRL_MEMSZ_1M		0x00080000
#define  GRC_LCLCTRL_MEMSZ_2M		0x000c0000
#define  GRC_LCLCTRL_MEMSZ_4M		0x00100000
#define  GRC_LCLCTRL_MEMSZ_8M		0x00140000
#define  GRC_LCLCTRL_MEMSZ_16M		0x00180000
#define  GRC_LCLCTRL_BANK_SELECT	0x00200000
#define  GRC_LCLCTRL_SSRAM_TYPE		0x00400000
#define  GRC_LCLCTRL_AUTO_SEEPROM	0x01000000
#define GRC_TIMER			0x0000680c
#define GRC_RX_CPU_EVENT		0x00006810
#define GRC_RX_TIMER_REF		0x00006814
#define GRC_RX_CPU_SEM			0x00006818
#define GRC_REMOTE_RX_CPU_ATTN		0x0000681c
#define GRC_TX_CPU_EVENT		0x00006820
#define GRC_TX_TIMER_REF		0x00006824
#define GRC_TX_CPU_SEM			0x00006828
#define GRC_REMOTE_TX_CPU_ATTN		0x0000682c
#define GRC_MEM_POWER_UP		0x00006830 /* 64-bit */
#define GRC_EEPROM_ADDR			0x00006838
#define  EEPROM_ADDR_WRITE		0x00000000
#define  EEPROM_ADDR_READ		0x80000000
#define  EEPROM_ADDR_COMPLETE		0x40000000
#define  EEPROM_ADDR_FSM_RESET		0x20000000
#define  EEPROM_ADDR_DEVID_MASK		0x1c000000
#define  EEPROM_ADDR_DEVID_SHIFT	26
#define  EEPROM_ADDR_START		0x02000000
#define  EEPROM_ADDR_CLKPERD_SHIFT	16
#define  EEPROM_ADDR_ADDR_MASK		0x0000ffff
#define  EEPROM_ADDR_ADDR_SHIFT		0
#define  EEPROM_DEFAULT_CLOCK_PERIOD	0x60
#define  EEPROM_CHIP_SIZE		(64 * 1024)
#define GRC_EEPROM_DATA			0x0000683c
#define GRC_EEPROM_CTRL			0x00006840
#define GRC_MDI_CTRL			0x00006844
#define GRC_SEEPROM_DELAY		0x00006848
/* 0x684c --> 0x6c00 unused */

/* 0x6c00 --> 0x7000 unused */

/* NVRAM Control registers */
#define NVRAM_CMD			0x00007000
#define  NVRAM_CMD_RESET		 0x00000001
#define  NVRAM_CMD_DONE			 0x00000008
#define  NVRAM_CMD_GO			 0x00000010
#define  NVRAM_CMD_WR			 0x00000020
#define  NVRAM_CMD_RD			 0x00000000
#define  NVRAM_CMD_ERASE		 0x00000040
#define  NVRAM_CMD_FIRST		 0x00000080
#define  NVRAM_CMD_LAST			 0x00000100
#define NVRAM_STAT			0x00007004
#define NVRAM_WRDATA			0x00007008
#define NVRAM_ADDR			0x0000700c
#define  NVRAM_ADDR_MSK			0x00ffffff
#define NVRAM_RDDATA			0x00007010
#define NVRAM_CFG1			0x00007014
#define  NVRAM_CFG1_FLASHIF_ENAB	 0x00000001
#define  NVRAM_CFG1_BUFFERED_MODE	 0x00000002
#define  NVRAM_CFG1_PASS_THRU		 0x00000004
#define  NVRAM_CFG1_BIT_BANG		 0x00000008
#define  NVRAM_CFG1_COMPAT_BYPASS	 0x80000000
#define NVRAM_CFG2			0x00007018
#define NVRAM_CFG3			0x0000701c
#define NVRAM_SWARB			0x00007020
#define  SWARB_REQ_SET0			 0x00000001
#define  SWARB_REQ_SET1			 0x00000002
#define  SWARB_REQ_SET2			 0x00000004
#define  SWARB_REQ_SET3			 0x00000008
#define  SWARB_REQ_CLR0			 0x00000010
#define  SWARB_REQ_CLR1			 0x00000020
#define  SWARB_REQ_CLR2			 0x00000040
#define  SWARB_REQ_CLR3			 0x00000080
#define  SWARB_GNT0			 0x00000100
#define  SWARB_GNT1			 0x00000200
#define  SWARB_GNT2			 0x00000400
#define  SWARB_GNT3			 0x00000800
#define  SWARB_REQ0			 0x00001000
#define  SWARB_REQ1			 0x00002000
#define  SWARB_REQ2			 0x00004000
#define  SWARB_REQ3			 0x00008000
#define    NVRAM_BUFFERED_PAGE_SIZE	   264
#define    NVRAM_BUFFERED_PAGE_POS	   9
/* 0x7024 --> 0x7400 unused */

/* 0x7400 --> 0x8000 unused */

/* 32K Window into NIC internal memory */
#define NIC_SRAM_WIN_BASE		0x00008000

/* Offsets into first 32k of NIC internal memory. */
#define NIC_SRAM_PAGE_ZERO		0x00000000
#define NIC_SRAM_SEND_RCB		0x00000100 /* 16 * TG3_BDINFO_... */
#define NIC_SRAM_RCV_RET_RCB		0x00000200 /* 16 * TG3_BDINFO_... */
#define NIC_SRAM_STATS_BLK		0x00000300
#define NIC_SRAM_STATUS_BLK		0x00000b00

#define NIC_SRAM_FIRMWARE_MBOX		0x00000b50
#define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1	 0x4B657654
#define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2	 0x4861764b /* !dma on linkchg */

#define NIC_SRAM_DATA_SIG		0x00000b54
#define  NIC_SRAM_DATA_SIG_MAGIC	 0x4b657654 /* ascii for 'KevT' */

#define NIC_SRAM_DATA_CFG			0x00000b58
#define  NIC_SRAM_DATA_CFG_LED_MODE_MASK	 0x0000000c
#define  NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN	 0x00000000
#define  NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD	 0x00000004
#define  NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN	 0x00000004
#define  NIC_SRAM_DATA_CFG_LED_LINK_SPD		 0x00000008
#define  NIC_SRAM_DATA_CFG_LED_OUTPUT		 0x00000008
#define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK	 0x00000030
#define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN	 0x00000000
#define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER	 0x00000010
#define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER	 0x00000020
#define  NIC_SRAM_DATA_CFG_WOL_ENABLE		 0x00000040
#define  NIC_SRAM_DATA_CFG_ASF_ENABLE		 0x00000080
#define  NIC_SRAM_DATA_CFG_EEPROM_WP		 0x00000100
#define  NIC_SRAM_DATA_CFG_MINI_PCI		 0x00001000
#define  NIC_SRAM_DATA_CFG_FIBER_WOL		 0x00004000

#define NIC_SRAM_DATA_PHY_ID		0x00000b74
#define  NIC_SRAM_DATA_PHY_ID1_MASK	 0xffff0000
#define  NIC_SRAM_DATA_PHY_ID2_MASK	 0x0000ffff

#define NIC_SRAM_FW_CMD_MBOX		0x00000b78
#define  FWCMD_NICDRV_ALIVE		 0x00000001
#define  FWCMD_NICDRV_PAUSE_FW		 0x00000002
#define  FWCMD_NICDRV_IPV4ADDR_CHG	 0x00000003
#define  FWCMD_NICDRV_IPV6ADDR_CHG	 0x00000004
#define  FWCMD_NICDRV_FIX_DMAR		 0x00000005
#define  FWCMD_NICDRV_FIX_DMAW		 0x00000006
#define NIC_SRAM_FW_CMD_LEN_MBOX	0x00000b7c
#define NIC_SRAM_FW_CMD_DATA_MBOX	0x00000b80
#define NIC_SRAM_FW_ASF_STATUS_MBOX	0x00000c00
#define NIC_SRAM_FW_DRV_STATE_MBOX	0x00000c04
#define  DRV_STATE_START		 0x00000001
#define  DRV_STATE_UNLOAD		 0x00000002
#define  DRV_STATE_WOL			 0x00000003
#define  DRV_STATE_SUSPEND		 0x00000004

#define NIC_SRAM_FW_RESET_TYPE_MBOX	0x00000c08

#define NIC_SRAM_MAC_ADDR_HIGH_MBOX	0x00000c14
#define NIC_SRAM_MAC_ADDR_LOW_MBOX	0x00000c18

#define NIC_SRAM_RX_MINI_BUFFER_DESC	0x00001000

#define NIC_SRAM_DMA_DESC_POOL_BASE	0x00002000
#define  NIC_SRAM_DMA_DESC_POOL_SIZE	 0x00002000
#define NIC_SRAM_TX_BUFFER_DESC		0x00004000 /* 512 entries */
#define NIC_SRAM_RX_BUFFER_DESC		0x00006000 /* 256 entries */
#define NIC_SRAM_RX_JUMBO_BUFFER_DESC	0x00007000 /* 256 entries */
#define NIC_SRAM_MBUF_POOL_BASE		0x00008000
#define  NIC