tg3.h

linux下从网卡远程启动

/* 0x3408 --> 0x3800 unused */

/* Mbuf cluster free registers */
#define MBFREE_MODE			0x00003800
#define  MBFREE_MODE_RESET		 0x00000001
#define  MBFREE_MODE_ENABLE		 0x00000002
#define MBFREE_STATUS			0x00003804
/* 0x3808 --> 0x3c00 unused */

/* Host coalescing control registers */
#define HOSTCC_MODE			0x00003c00
#define  HOSTCC_MODE_RESET		 0x00000001
#define  HOSTCC_MODE_ENABLE		 0x00000002
#define  HOSTCC_MODE_ATTN		 0x00000004
#define  HOSTCC_MODE_NOW		 0x00000008
#define  HOSTCC_MODE_FULL_STATUS	 0x00000000
#define  HOSTCC_MODE_64BYTE		 0x00000080
#define  HOSTCC_MODE_32BYTE		 0x00000100
#define  HOSTCC_MODE_CLRTICK_RXBD	 0x00000200
#define  HOSTCC_MODE_CLRTICK_TXBD	 0x00000400
#define  HOSTCC_MODE_NOINT_ON_NOW	 0x00000800
#define  HOSTCC_MODE_NOINT_ON_FORCE	 0x00001000
#define HOSTCC_STATUS			0x00003c04
#define  HOSTCC_STATUS_ERROR_ATTN	 0x00000004
#define HOSTCC_RXCOL_TICKS		0x00003c08
#define  LOW_RXCOL_TICKS		 0x00000032
#define  DEFAULT_RXCOL_TICKS		 0x00000048
#define  HIGH_RXCOL_TICKS		 0x00000096
#define HOSTCC_TXCOL_TICKS		0x00003c0c
#define  LOW_TXCOL_TICKS		 0x00000096
#define  DEFAULT_TXCOL_TICKS		 0x0000012c
#define  HIGH_TXCOL_TICKS		 0x00000145
#define HOSTCC_RXMAX_FRAMES		0x00003c10
#define  LOW_RXMAX_FRAMES		 0x00000005
#define  DEFAULT_RXMAX_FRAMES		 0x00000008
#define  HIGH_RXMAX_FRAMES		 0x00000012
#define HOSTCC_TXMAX_FRAMES		0x00003c14
#define  LOW_TXMAX_FRAMES		 0x00000035
#define  DEFAULT_TXMAX_FRAMES		 0x0000004b
#define  HIGH_TXMAX_FRAMES		 0x00000052
#define HOSTCC_RXCOAL_TICK_INT		0x00003c18
#define  DEFAULT_RXCOAL_TICK_INT	 0x00000019
#define HOSTCC_TXCOAL_TICK_INT		0x00003c1c
#define  DEFAULT_TXCOAL_TICK_INT	 0x00000019
#define HOSTCC_RXCOAL_MAXF_INT		0x00003c20
#define  DEFAULT_RXCOAL_MAXF_INT	 0x00000005
#define HOSTCC_TXCOAL_MAXF_INT		0x00003c24
#define  DEFAULT_TXCOAL_MAXF_INT	 0x00000005
#define HOSTCC_STAT_COAL_TICKS		0x00003c28
#define  DEFAULT_STAT_COAL_TICKS	 0x000f4240
/* 0x3c2c --> 0x3c30 unused */
#define HOSTCC_STATS_BLK_HOST_ADDR	0x00003c30 /* 64-bit */
#define HOSTCC_STATUS_BLK_HOST_ADDR	0x00003c38 /* 64-bit */
#define HOSTCC_STATS_BLK_NIC_ADDR	0x00003c40
#define HOSTCC_STATUS_BLK_NIC_ADDR	0x00003c44
#define HOSTCC_FLOW_ATTN		0x00003c48
/* 0x3c4c --> 0x3c50 unused */
#define HOSTCC_JUMBO_CON_IDX		0x00003c50
#define HOSTCC_STD_CON_IDX		0x00003c54
#define HOSTCC_MINI_CON_IDX		0x00003c58
/* 0x3c5c --> 0x3c80 unused */
#define HOSTCC_RET_PROD_IDX_0		0x00003c80
#define HOSTCC_RET_PROD_IDX_1		0x00003c84
#define HOSTCC_RET_PROD_IDX_2		0x00003c88
#define HOSTCC_RET_PROD_IDX_3		0x00003c8c
#define HOSTCC_RET_PROD_IDX_4		0x00003c90
#define HOSTCC_RET_PROD_IDX_5		0x00003c94
#define HOSTCC_RET_PROD_IDX_6		0x00003c98
#define HOSTCC_RET_PROD_IDX_7		0x00003c9c
#define HOSTCC_RET_PROD_IDX_8		0x00003ca0
#define HOSTCC_RET_PROD_IDX_9		0x00003ca4
#define HOSTCC_RET_PROD_IDX_10		0x00003ca8
#define HOSTCC_RET_PROD_IDX_11		0x00003cac
#define HOSTCC_RET_PROD_IDX_12		0x00003cb0
#define HOSTCC_RET_PROD_IDX_13		0x00003cb4
#define HOSTCC_RET_PROD_IDX_14		0x00003cb8
#define HOSTCC_RET_PROD_IDX_15		0x00003cbc
#define HOSTCC_SND_CON_IDX_0		0x00003cc0
#define HOSTCC_SND_CON_IDX_1		0x00003cc4
#define HOSTCC_SND_CON_IDX_2		0x00003cc8
#define HOSTCC_SND_CON_IDX_3		0x00003ccc
#define HOSTCC_SND_CON_IDX_4		0x00003cd0
#define HOSTCC_SND_CON_IDX_5		0x00003cd4
#define HOSTCC_SND_CON_IDX_6		0x00003cd8
#define HOSTCC_SND_CON_IDX_7		0x00003cdc
#define HOSTCC_SND_CON_IDX_8		0x00003ce0
#define HOSTCC_SND_CON_IDX_9		0x00003ce4
#define HOSTCC_SND_CON_IDX_10		0x00003ce8
#define HOSTCC_SND_CON_IDX_11		0x00003cec
#define HOSTCC_SND_CON_IDX_12		0x00003cf0
#define HOSTCC_SND_CON_IDX_13		0x00003cf4
#define HOSTCC_SND_CON_IDX_14		0x00003cf8
#define HOSTCC_SND_CON_IDX_15		0x00003cfc
/* 0x3d00 --> 0x4000 unused */

/* Memory arbiter control registers */
#define MEMARB_MODE			0x00004000
#define  MEMARB_MODE_RESET		 0x00000001
#define  MEMARB_MODE_ENABLE		 0x00000002
#define MEMARB_STATUS			0x00004004
#define MEMARB_TRAP_ADDR_LOW		0x00004008
#define MEMARB_TRAP_ADDR_HIGH		0x0000400c
/* 0x4010 --> 0x4400 unused */

/* Buffer manager control registers */
#define BUFMGR_MODE			0x00004400
#define  BUFMGR_MODE_RESET		 0x00000001
#define  BUFMGR_MODE_ENABLE		 0x00000002
#define  BUFMGR_MODE_ATTN_ENABLE	 0x00000004
#define  BUFMGR_MODE_BM_TEST		 0x00000008
#define  BUFMGR_MODE_MBLOW_ATTN_ENAB	 0x00000010
#define BUFMGR_STATUS			0x00004404
#define  BUFMGR_STATUS_ERROR		 0x00000004
#define  BUFMGR_STATUS_MBLOW		 0x00000010
#define BUFMGR_MB_POOL_ADDR		0x00004408
#define BUFMGR_MB_POOL_SIZE		0x0000440c
#define BUFMGR_MB_RDMA_LOW_WATER	0x00004410
#define  DEFAULT_MB_RDMA_LOW_WATER	 0x00000050
#define  DEFAULT_MB_RDMA_LOW_WATER_5705	 0x00000000
#define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
#define BUFMGR_MB_MACRX_LOW_WATER	0x00004414
#define  DEFAULT_MB_MACRX_LOW_WATER	  0x00000020
#define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
#define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
#define BUFMGR_MB_HIGH_WATER		0x00004418
#define  DEFAULT_MB_HIGH_WATER		 0x00000060
#define  DEFAULT_MB_HIGH_WATER_5705	 0x00000060
#define  DEFAULT_MB_HIGH_WATER_JUMBO	 0x0000017c
#define BUFMGR_RX_MB_ALLOC_REQ		0x0000441c
#define  BUFMGR_MB_ALLOC_BIT		 0x10000000
#define BUFMGR_RX_MB_ALLOC_RESP		0x00004420
#define BUFMGR_TX_MB_ALLOC_REQ		0x00004424
#define BUFMGR_TX_MB_ALLOC_RESP		0x00004428
#define BUFMGR_DMA_DESC_POOL_ADDR	0x0000442c
#define BUFMGR_DMA_DESC_POOL_SIZE	0x00004430
#define BUFMGR_DMA_LOW_WATER		0x00004434
#define  DEFAULT_DMA_LOW_WATER		 0x00000005
#define BUFMGR_DMA_HIGH_WATER		0x00004438
#define  DEFAULT_DMA_HIGH_WATER		 0x0000000a
#define BUFMGR_RX_DMA_ALLOC_REQ		0x0000443c
#define BUFMGR_RX_DMA_ALLOC_RESP	0x00004440
#define BUFMGR_TX_DMA_ALLOC_REQ		0x00004444
#define BUFMGR_TX_DMA_ALLOC_RESP	0x00004448
#define BUFMGR_HWDIAG_0			0x0000444c
#define BUFMGR_HWDIAG_1			0x00004450
#define BUFMGR_HWDIAG_2			0x00004454
/* 0x4458 --> 0x4800 unused */

/* Read DMA control registers */
#define RDMAC_MODE			0x00004800
#define  RDMAC_MODE_RESET		 0x00000001
#define  RDMAC_MODE_ENABLE		 0x00000002
#define  RDMAC_MODE_TGTABORT_ENAB	 0x00000004
#define  RDMAC_MODE_MSTABORT_ENAB	 0x00000008
#define  RDMAC_MODE_PARITYERR_ENAB	 0x00000010
#define  RDMAC_MODE_ADDROFLOW_ENAB	 0x00000020
#define  RDMAC_MODE_FIFOOFLOW_ENAB	 0x00000040
#define  RDMAC_MODE_FIFOURUN_ENAB	 0x00000080
#define  RDMAC_MODE_FIFOOREAD_ENAB	 0x00000100
#define  RDMAC_MODE_LNGREAD_ENAB	 0x00000200
#define  RDMAC_MODE_SPLIT_ENABLE	 0x00000800
#define  RDMAC_MODE_SPLIT_RESET		 0x00001000
#define  RDMAC_MODE_FIFO_SIZE_128	 0x00020000
#define  RDMAC_MODE_FIFO_LONG_BURST	 0x00030000
#define RDMAC_STATUS			0x00004804
#define  RDMAC_STATUS_TGTABORT		 0x00000004
#define  RDMAC_STATUS_MSTABORT		 0x00000008
#define  RDMAC_STATUS_PARITYERR		 0x00000010
#define  RDMAC_STATUS_ADDROFLOW		 0x00000020
#define  RDMAC_STATUS_FIFOOFLOW		 0x00000040
#define  RDMAC_STATUS_FIFOURUN		 0x00000080
#define  RDMAC_STATUS_FIFOOREAD		 0x00000100
#define  RDMAC_STATUS_LNGREAD		 0x00000200
/* 0x4808 --> 0x4c00 unused */

/* Write DMA control registers */
#define WDMAC_MODE			0x00004c00
#define  WDMAC_MODE_RESET		 0x00000001
#define  WDMAC_MODE_ENABLE		 0x00000002
#define  WDMAC_MODE_TGTABORT_ENAB	 0x00000004
#define  WDMAC_MODE_MSTABORT_ENAB	 0x00000008
#define  WDMAC_MODE_PARITYERR_ENAB	 0x00000010
#define  WDMAC_MODE_ADDROFLOW_ENAB	 0x00000020
#define  WDMAC_MODE_FIFOOFLOW_ENAB	 0x00000040
#define  WDMAC_MODE_FIFOURUN_ENAB	 0x00000080
#define  WDMAC_MODE_FIFOOREAD_ENAB	 0x00000100
#define  WDMAC_MODE_LNGREAD_ENAB	 0x00000200
#define  WDMAC_MODE_RX_ACCEL	 	 0x00000400
#define WDMAC_STATUS			0x00004c04
#define  WDMAC_STATUS_TGTABORT		 0x00000004
#define  WDMAC_STATUS_MSTABORT		 0x00000008
#define  WDMAC_STATUS_PARITYERR		 0x00000010
#define  WDMAC_STATUS_ADDROFLOW		 0x00000020
#define  WDMAC_STATUS_FIFOOFLOW		 0x00000040
#define  WDMAC_STATUS_FIFOURUN		 0x00000080
#define  WDMAC_STATUS_FIFOOREAD		 0x00000100
#define  WDMAC_STATUS_LNGREAD		 0x00000200
/* 0x4c08 --> 0x5000 unused */

/* Per-cpu register offsets (arm9) */
#define CPU_MODE			0x00000000
#define  CPU_MODE_RESET			 0x00000001
#define  CPU_MODE_HALT			 0x00000400
#define CPU_STATE			0x00000004
#define CPU_EVTMASK			0x00000008
/* 0xc --> 0x1c reserved */
#define CPU_PC				0x0000001c
#define CPU_INSN			0x00000020
#define CPU_SPAD_UFLOW			0x00000024
#define CPU_WDOG_CLEAR			0x00000028
#define CPU_WDOG_VECTOR			0x0000002c
#define CPU_WDOG_PC			0x00000030
#define CPU_HW_BP			0x00000034
/* 0x38 --> 0x44 unused */
#define CPU_WDOG_SAVED_STATE		0x00000044
#define CPU_LAST_BRANCH_ADDR		0x00000048
#define CPU_SPAD_UFLOW_SET		0x0000004c
/* 0x50 --> 0x200 unused */
#define CPU_R0				0x00000200
#define CPU_R1				0x00000204
#define CPU_R2				0x00000208
#define CPU_R3				0x0000020c
#define CPU_R4				0x00000210
#define CPU_R5				0x00000214
#define CPU_R6				0x00000218
#define CPU_R7				0x0000021c
#define CPU_R8				0x00000220
#define CPU_R9				0x00000224
#define CPU_R10				0x00000228
#define CPU_R11				0x0000022c
#define CPU_R12				0x00000230
#define CPU_R13				0x00000234
#define CPU_R14				0x00000238
#define CPU_R15				0x0000023c
#define CPU_R16				0x00000240
#define CPU_R17				0x00000244
#define CPU_R18				0x00000248
#define CPU_R19				0x0000024c
#define CPU_R20				0x00000250
#define CPU_R21				0x00000254
#define CPU_R22				0x00000258
#define CPU_R23				0x0000025c
#define CPU_R24				0x00000260
#define CPU_R25				0x00000264
#define CPU_R26				0x00000268
#define CPU_R27				0x0000026c
#define CPU_R28				0x00000270
#define CPU_R29				0x00000274
#define CPU_R30				0x00000278
#define CPU_R31				0x0000027c
/* 0x280 --> 0x400 unused */

#define RX_CPU_BASE			0x00005000
#define TX_CPU_BASE			0x00005400

/* Mailboxes */
#define GRCMBOX_INTERRUPT_0		0x00005800 /* 64-bit */
#define GRCMBOX_INTERRUPT_1		0x00005808 /* 64-bit */
#define GRCMBOX_INTERRUPT_2		0x00005810 /* 64-bit */
#define GRCMBOX_INTERRUPT_3		0x00005818 /* 64-bit */
#define GRCMBOX_GENERAL_0		0x00005820 /* 64-bit */
#define GRCMBOX_GENERAL_1		0x00005828 /* 64-bit */
#define GRCMBOX_GENERAL_2		0x00005830 /* 64-bit */
#define GRCMBOX_GENERAL_3		0x00005838 /* 64-bit */
#define GRCMBOX_GENERAL_4		0x00005840 /* 64-bit */
#define GRCMBOX_GENERAL_5		0x00005848 /* 64-bit */
#define GRCMBOX_GENERAL_6		0x00005850 /* 64-bit */
#define GRCMBOX_GENERAL_7		0x00005858 /* 64-bit */
#define GRCMBOX_RELOAD_STAT		0x00005860 /* 64-bit */
#define GRCMBOX_RCVSTD_PROD_IDX		0x00005868 /* 64-bit */
#define GRCMBOX_RCVJUMBO_PROD_IDX	0x00005870 /* 64-bit */
#define GRCMBOX_RCVMINI_PROD_IDX	0x00005878 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_0	0x00005880 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_1	0x00005888 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_2	0x00005890 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_3	0x00005898 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_4	0x000058a0 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_5	0x000058a8 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_6	0x000058b0 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_7	0x000058b8 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_8	0x000058c0 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_9	0x000058c8 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_10	0x000058d0 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_11	0x000058d8 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_12	0x000058e0 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_13	0x000058e8 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_14	0x000058f0 /* 64-bit */
#define GRCMBOX_RCVRET_CON_IDX_15	0x000058f8 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_0	0x00005900 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_1	0x00005908 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_2	0x00005910 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_3	0x00005918 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_4	0x00005920 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_5	0x00005928 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_6	0x00005930 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_7	0x00005938 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_8	0x00005940 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_9	0x00005948 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_10	0x00005950 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_11	0x00005958 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_12	0x00005960 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_13	0x00005968 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_14	0x00005970 /* 64-bit */
#define GRCMBOX_SNDHOST_PROD_IDX_15	0x00005978 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_0	0x00005980 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_1	0x00005988 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_2	0x00005990 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_3	0x00005998 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_4	0x000059a0 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_5	0x000059a8 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_6	0x000059b0 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_7	0x000059b8 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_8	0x000059c0 /* 64-bit */
#define GRCMBOX_SNDNIC_PROD_IDX_9	0x000059c8 /* 64-bit */