i82365.h

linux下从网卡远程启动

/*
 * i82365.h 1.15 1999/10/25 20:03:34
 *
 * The contents of this file may be used under the
 * terms of the GNU General Public License version 2 (the "GPL").
 *
 * Software distributed under the License is distributed on an "AS IS"
 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
 * the License for the specific language governing rights and
 * limitations under the License. 
 *
 * The initial developer of the original code is David A. Hinds
 * <[e-mail]>.  Portions created by David A. Hinds
 * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
 */

#ifndef _LINUX_I82365_H
#define _LINUX_I82365_H

/* register definitions for the Intel 82365SL PCMCIA controller */

/* Offsets for PCIC registers */
#define I365_IDENT	0x00	/* Identification and revision */
#define I365_STATUS	0x01	/* Interface status */
#define I365_POWER	0x02	/* Power and RESETDRV control */
#define I365_INTCTL	0x03	/* Interrupt and general control */
#define I365_CSC	0x04	/* Card status change */
#define I365_CSCINT	0x05	/* Card status change interrupt control */
#define I365_ADDRWIN	0x06	/* Address window enable */
#define I365_IOCTL	0x07	/* I/O control */
#define I365_GENCTL	0x16	/* Card detect and general control */
#define I365_GBLCTL	0x1E	/* Global control register */

/* Offsets for I/O and memory window registers */
#define I365_IO(map)	(0x08+((map)<<2))
#define I365_MEM(map)	(0x10+((map)<<3))
#define I365_W_START	0
#define I365_W_STOP	2
#define I365_W_OFF	4

/* Flags for I365_STATUS */
#define I365_CS_BVD1	0x01
#define I365_CS_STSCHG	0x01
#define I365_CS_BVD2	0x02
#define I365_CS_SPKR	0x02
#define I365_CS_DETECT	0x0C
#define I365_CS_WRPROT	0x10
#define I365_CS_READY	0x20	/* Inverted */
#define I365_CS_POWERON	0x40
#define I365_CS_GPI	0x80

/* Flags for I365_POWER */
#define I365_PWR_OFF	0x00	/* Turn off the socket */
#define I365_PWR_OUT	0x80	/* Output enable */
#define I365_PWR_NORESET 0x40	/* Disable RESETDRV on resume */
#define I365_PWR_AUTO	0x20	/* Auto pwr switch enable */
#define I365_VCC_MASK	0x18	/* Mask for turning off Vcc */
/* There are different layouts for B-step and DF-step chips: the B
   step has independent Vpp1/Vpp2 control, and the DF step has only
   Vpp1 control, plus 3V control */
#define I365_VCC_5V	0x10	/* Vcc = 5.0v */
#define I365_VCC_3V	0x18	/* Vcc = 3.3v */
#define I365_VPP2_MASK	0x0c	/* Mask for turning off Vpp2 */
#define I365_VPP2_5V	0x04	/* Vpp2 = 5.0v */
#define I365_VPP2_12V	0x08	/* Vpp2 = 12.0v */
#define I365_VPP1_MASK	0x03	/* Mask for turning off Vpp1 */
#define I365_VPP1_5V	0x01	/* Vpp2 = 5.0v */
#define I365_VPP1_12V	0x02	/* Vpp2 = 12.0v */

/* Flags for I365_INTCTL */
#define I365_RING_ENA	0x80
#define I365_PC_RESET	0x40
#define I365_PC_IOCARD	0x20
#define I365_INTR_ENA	0x10
#define I365_IRQ_MASK	0x0F

/* Flags for I365_CSC and I365_CSCINT*/
#define I365_CSC_BVD1	0x01
#define I365_CSC_STSCHG	0x01
#define I365_CSC_BVD2	0x02
#define I365_CSC_READY	0x04
#define I365_CSC_DETECT	0x08
#define I365_CSC_ANY	0x0F
#define I365_CSC_GPI	0x10

/* Flags for I365_ADDRWIN */
#define I365_ENA_IO(map)	(0x40 << (map))
#define I365_ENA_MEM(map)	(0x01 << (map))

/* Flags for I365_IOCTL */
#define I365_IOCTL_MASK(map)	(0x0F << (map<<2))
#define I365_IOCTL_WAIT(map)	(0x08 << (map<<2))
#define I365_IOCTL_0WS(map)	(0x04 << (map<<2))
#define I365_IOCTL_IOCS16(map)	(0x02 << (map<<2))
#define I365_IOCTL_16BIT(map)	(0x01 << (map<<2))

/* Flags for I365_GENCTL */
#define I365_CTL_16DELAY	0x01
#define I365_CTL_RESET		0x02
#define I365_CTL_GPI_ENA	0x04
#define I365_CTL_GPI_CTL	0x08
#define I365_CTL_RESUME		0x10
#define I365_CTL_SW_IRQ		0x20

/* Flags for I365_GBLCTL */
#define I365_GBL_PWRDOWN	0x01
#define I365_GBL_CSC_LEV	0x02
#define I365_GBL_WRBACK		0x04
#define I365_GBL_IRQ_0_LEV	0x08
#define I365_GBL_IRQ_1_LEV	0x10

/* Flags for memory window registers */
#define I365_MEM_16BIT	0x8000	/* In memory start high byte */
#define I365_MEM_0WS	0x4000
#define I365_MEM_WS1	0x8000	/* In memory stop high byte */
#define I365_MEM_WS0	0x4000
#define I365_MEM_WRPROT	0x8000	/* In offset high byte */
#define I365_MEM_REG	0x4000

#define I365_REG(slot, reg)	(((slot) << 6) + reg)

#endif /* _LINUX_I82365_H */

//*****************************************************************************
//*****************************************************************************
//*****************************************************************************
//*****************************************************************************
//*****************************************************************************
// Beginning vg468.h (for VADEM chipset)

#ifndef _LINUX_VG468_H
#define _LINUX_VG468_H

/* Special bit in I365_IDENT used for Vadem chip detection */
#define I365_IDENT_VADEM        0x08

/* Special definitions in I365_POWER */
#define VG468_VPP2_MASK         0x0c
#define VG468_VPP2_5V           0x04
#define VG468_VPP2_12V          0x08

/* Unique Vadem registers */
#define VG469_VSENSE            0x1f    /* Card voltage sense */
#define VG469_VSELECT           0x2f    /* Card voltage select */
#define VG468_CTL               0x38    /* Control register */
#define VG468_TIMER             0x39    /* Timer control */
#define VG468_MISC              0x3a    /* Miscellaneous */
#define VG468_GPIO_CFG          0x3b    /* GPIO configuration */
#define VG469_EXT_MODE          0x3c    /* Extended mode register */
#define VG468_SELECT            0x3d    /* Programmable chip select */
#define VG468_SELECT_CFG        0x3e    /* Chip select configuration */
#define VG468_ATA               0x3f    /* ATA control */

/* Flags for VG469_VSENSE */
#define VG469_VSENSE_A_VS1      0x01
#define VG469_VSENSE_A_VS2      0x02
#define VG469_VSENSE_B_VS1      0x04
#define VG469_VSENSE_B_VS2      0x08

/* Flags for VG469_VSELECT */
#define VG469_VSEL_VCC          0x03
#define VG469_VSEL_5V           0x00
#define VG469_VSEL_3V           0x03
#define VG469_VSEL_MAX          0x0c
#define VG469_VSEL_EXT_STAT     0x10
#define VG469_VSEL_EXT_BUS      0x20
#define VG469_VSEL_MIXED        0x40
#define VG469_VSEL_ISA          0x80

/* Flags for VG468_CTL */
#define VG468_CTL_SLOW          0x01    /* 600ns memory timing */
#define VG468_CTL_ASYNC         0x02    /* Asynchronous bus clocking */
#define VG468_CTL_TSSI          0x08    /* Tri-state some outputs */
#define VG468_CTL_DELAY         0x10    /* Card detect debounce */
#define VG468_CTL_INPACK        0x20    /* Obey INPACK signal? */
#define VG468_CTL_POLARITY      0x40    /* VCCEN polarity */
#define VG468_CTL_COMPAT        0x80    /* Compatibility stuff */

#define VG469_CTL_WS_COMPAT     0x04    /* Wait state compatibility */
#define VG469_CTL_STRETCH       0x10    /* LED stretch */

/* Flags for VG468_TIMER */
#define VG468_TIMER_ZEROPWR     0x10    /* Zero power control */
#define VG468_TIMER_SIGEN       0x20    /* Power up */
#define VG468_TIMER_STATUS      0x40    /* Activity timer status */
#define VG468_TIMER_RES         0x80    /* Timer resolution */
#define VG468_TIMER_MASK        0x0f    /* Activity timer timeout */

/* Flags for VG468_MISC */
#define VG468_MISC_GPIO         0x04    /* General-purpose IO */
#define VG468_MISC_DMAWSB       0x08    /* DMA wait state control */
#define VG469_MISC_LEDENA       0x10    /* LED enable */
#define VG468_MISC_VADEMREV     0x40    /* Vadem revision control */
#define VG468_MISC_UNLOCK       0x80    /* Unique register lock */

/* Flags for VG469_EXT_MODE_A */
#define VG469_MODE_VPPST        0x03    /* Vpp steering control */
#define VG469_MODE_INT_SENSE    0x04    /* Internal voltage sense */
#define VG469_MODE_CABLE        0x08
#define VG469_MODE_COMPAT       0x10    /* i82365sl B or DF step */
#define VG469_MODE_TEST         0x20
#define VG469_MODE_RIO          0x40    /* Steer RIO to INTR? */

/* Flags for VG469_EXT_MODE_B */
#define VG469_MODE_B_3V         0x01    /* 3.3v for socket B */

#endif /* _LINUX_VG468_H */


//*****************************************************************************
//*****************************************************************************
//*****************************************************************************
//*****************************************************************************
//*****************************************************************************
// Beginning ricoh.h (RICOH chipsets)

#ifndef _LINUX_RICOH_H
#define _LINUX_RICOH_H


#define RF5C_MODE_CTL           0x1f    /* Mode control */
#define RF5C_PWR_CTL            0x2f    /* Mixed voltage control */
#define RF5C_CHIP_ID            0x3a    /* Chip identification */
#define RF5C_MODE_CTL_3         0x3b    /* Mode control 3 */

/* I/O window address offset */