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PCL4W Users Manual Page 19
6.5 Transmitter Interrupts
Transmitter interrupts are supported by the library. Separate libraries are
provided, one with transmitter interrupts enabled and one without. When
transmitter interrupts are NOT enabled, the following logic occurs every
time you call SioPutc():
1. Wait for transmit buffer to become empty. The transmit buffer may not
be empty if the previous transmit is not completed (the UART breaks down the
byte & sends 1 bit at a time). 2. When the transmit buffer is empty, the
byte from the SioPutc() call is loaded into the transmit buffer and control
is returned to the caller.
Note that you can not write to the UART any faster the the UART baud rate.
When transmitter interrupts are enabled, the byte from SioPutc() is put into
a previously prepared (by SioTxQue) transmitter queue. The interrupt service
routine fetches bytes from this queue as soon as the previous byte has been
sent.
While you can now call SioPutc() faster than the baud rate, bytes are still
transmitted at the given baud rate.
The above sounds like transmitter interrupts are the way to go.
Unfortunately, this is usually NOT the case. Most applications will perform
better if transmitter interrupts are NOT enabled.
The reason is that transmitter interrupts double the amount of code in the
time critical interrupt service routine. While the library is processing a
transmitter interrupt (which can take a while), incoming bytes can not be
processed. What this means is that a given machine can run at a higher baud
rate without transmitter interrupts. This problem is compounded when running
multiple ports simultaniously.
However, there are a few application areas where transmitter interrupts are
preferable. If your application will be transmitting blocks of data at
fairly slow baud rates you might profit from enabling transmitter interrupts
provided that there is something else for the processor to do (which is NOT
the case in most protocols).
However, if you are using 16550 UARTS (which have 16 byte on-chip transmit
and receive buffers rather that the 1 byte buffers on the 8250 and 16450
UARTS), you may want to use the library version with interrupts enabled
provided that you enable the 16550 UART with the SioFIFO() function.
PCL4W Users Manual Page 20
6.6 RS-232 Signals
RS-232 is the name of the serial data interface standard used to connect
computers to modems. Most IBM compatible computers are built with at least
one serial port and use either DB9 (9 pin) or DB25 (25 pin) connectors.
A summary of these pins and their function follows. For more detailed
information, refer to one of the many books dealing with RS-232 interfacing.
Signal Ground Pin 7 (DB25), Pin 5 (DB9)
The SG line is used as the common signal ground, and must always be
connected.
Transmit Data Pin 2 (DB25), Pin 3 (DB9)
The TX line is used to carry data from the computer to the modem.
Receive Data Pin 3 (DB25), Pin 2 (DB9)
The RX line is used to carry data from the modem to the computer.
Data Terminal Ready Pin 20 (DB25), Pin 4 (DB9)
The DTR line is used by the computer to signal the modem that it is ready.
DTR should be set high when talking to a modem.
Data Set Ready Pin 6 (DB25), Pin 6 (DB9)
The DSR line is used by the modem to signal the computer that it is ready.
Request to Send Pin 4 (DB25), Pin 7 (DB9)
The RTS line is used to "turn the line around" in half duplex modems, and
for hardware flow control in most modems that require flow control.
Clear to Send Pin 5 (DB25), Pin 8 (DB9)
The CTS line is used to "turn the line around" in half duplex modems, and
for hardware flow control in most modems that require flow control.
Data Carrier Detect Pin 8 (DB25), Pin 1 (DB9)
The DCD line is used by the modem to signal the computer that a data carrier
signal is present.
Ring Indicator Pin 22 (DB25), Pin 9 (DB9)
The RI line is asserted when a 'ring' occurs.
PCL4W Users Manual Page 21
6.7 National INS8250, INS16450, and INS16550 UARTs
The Personal Communications Library is based on the standard National
INS8250, INS16450, and INS16550 UARTs. The 8250 was the original UART used
in the IBM PC, whereas the 16450 is a faster version found on most 286 & up
machines. The 16550 contains a 16 byte FIFO to further reduce communications
overhead. These UARTs consists of 8 register ports as follows:
Offset R/W Register
0 R/W Receiver (read) / Transmitter (write)
1 R/W Interrupt Enable (read)
2 R Interrupt Identification
2 W FIFO control (INS16550 only)
3 R/W Data Format (Line Control)
4 R/W RS-232 (Modem) Control
5 R/W Line Status
6 R/W RS-232 (Modem) Status
7 R/W Not used.
For the standard PC ports (not DigiBoard ports), the UART registers are
based at 3F8h (COM1), 2F8h (COM2), 3E8h (COM3), and 2E8h (COM4). COM1 and
COM3 share interrupt request line IRQ4 while COM2 and COM4 share request
line IRQ3. This means that COM1 and COM3 can't be used concurrently.
Similarly for COM2 and COM4.
However, standard PC ports may be re-configured to use other UART addresses
and IRQ assignments. Refer to the SioPorts(), SioUART(), and SioIRQ()
functions.
If you have a DigiBoard PC/4 (or PC/8) installed, you will have 4 (or 8)
additional ports using INS16450 or INS16550 UARTS. The default DigiBoard
ports are located at 100h, 108h, 110h & 118h for the PC/4 continuing with
120h 128h, 130h & 138h for the PC/8. IRQ3 is the default for all ports.
Four sources of interrupts are possible with the 8250 and 16550: (1)
receiver error or BREAK, (2) receiver data ready, (3) ready to transmit, and
(4) RS232 input. These four sources of interrupts are summarized as
follows:
Source of Interrupt Action Required to Clear
Receiver error or BREAK. Read Line Status register.
Receiver data. Read data from data register.
Transmitter Buffer Empty. Write to data register or read IID reg.
RS232 Input. Read Modem Status register.
If you are not familiar with UARTS, several good books are available. Refer
to the Serial Communications chapter for recommendations. Although a
knowledge of the 8250/16450/16550 is not necessary to use PCL4W, a general
knowledge of the theory of asynchronous serial communications is helpfull.
PCL4W Users Manual Page 22
6.8 Register Summary
REG 0 : Data Register
Reading from the data register fetches the next input byte, once it is
ready. Writing to the data register transmits the byte written to it over
the serial line.
REG 1 : Interrupt Enable
The Interrupt Enable register enables each of four types of interrupts when
the appropriate bit is set to a one.
bit 3 : Enable interrupt on RS232 input.
bit 2 : Enable interrupt on receiver error or break.
bit 1 : Enable interrupt on transmitter buffer empty (TBE).
bit 0 : Enable interrupt on received data (RxRDY).
REG 2 : Interrupt Identification (IID)
Reading the Interrupt Identification (read only) register once an interrupt
has occurred identifies the interrupt as follows:
Bit 2 Bit 1 Bit 0 Priority Interrupt
0 0 1 none none
1 1 0 0 (high) Serialization or break.
1 0 0 1 Received data.
0 1 0 2 Transmitter Buffer Empty.
0 0 0 3 (low) RS232 Input.
In the INS16650, REG 2 (write only) is also the FIFO control register.
Writing bits 6 & 7 will set the FIFO trigger level (number of bytes received
before an interrupt is generated).
Bit 7 Bit 6 Trigger Bit 7 Bit 6 Trigger
0 0 1 byte 1 0 8 bytes
0 1 4 bytes 1 1 14 bytes
REG 3 : Line Control
RS232 line parameters are selected by writing to this register.
bit 7 : DLAB = 0
bit 6 : BREAK on(1), off(0).
bits 5-3: Parity None(000),ODD(001),EVEN(011),MARK(101),SPACE(111)
bit 2 : One stop bit(0), two stop bits(1).
bits 1-0: Data bits = 5 (00), 6(01), 7(10), 8(11).
When the Divisor Latch Access Bit (DLAB) is 1, registers 0 and 1 become the
LS and MS bytes of the Baud Rate Divisor registers.
Baud Divisor Baud Divisor Baud Divisor
300 0180 4800 0018 38400 0003
1200 0060 9600 000C 57600 0002
2400 0030 19200 0006 115200 0001
PCL4W Users Manual Page 23
REG 4 : Modem Control
RTS, DTR, loopback testing, and General Purpose Outputs #1 and #2 are
controlled by the Modem Control register as follows:
bit 4 : Enable local loopback.
bit 3 : Enable GP02. Necessary for 8250 interrupts.
bit 2 : Enable GP01.
bit 1 : Set / clear RTS.
bit 0 : Set / clear DTR.
REG 5 : Line Status
Reading the Line Status register provides status information as follows (1
for TRUE, 0 for FALSE) :
bit 6 : Transmitter Empty.
bit 5 : Transmitter Buffer Empty (TBE).
bit 4 : BREAK detect.
bit 3 : Framing error.
bit 2 : Parity error.
bit 1 : Overrun error.
bit 0 : Data Ready.
REG 6 : Modem Status
Reading the Modem Status register provides the following status information
(1 for TRUE, 0 for FALSE) :
bit 7 : DCD status.
bit 6 : RI status.
bit 5 : DSR status.
bit 4 : CTS status.
bit 3 : Delta DCD status.
bit 2 : Delta RI status.
bit 1 : Delta DSR status.
bit 0 : Delta CTS status.
The delta bits (bits 0 through 3) are set whenever one of the status bits
(bits 4 through 7) changes (from 0 to 1 or from 1 to 0) since the last time
the Modem Status register was rea⌨️ 快捷键说明
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