mr24io.h

3 phase motor driver source code with freescale MCU

/***********************************************************************
 * HEADER_START                                                        *
 *                                                                     *
 *      Name:           Mr24io.h                                       *
 *      Project:        Sensorless BLDC Motor HC08                     *
 *      Description:    MC68HC08MR24 registers map include file        *
 *      Processor:      HC08MR24                                       *
 *      HW:                                                            *
 *      Revision:       0.1                                            *
 *      Date:           26th March 1999                                *
 *      Compiler:       C crosscompiler HIWARE HICROSS+Version 5.0.6   *
 *      Author:         Libor Prokop, Radim Visinka                    *
 *      Company:        Motorola SPS                                   *
 *                      Roznov System Application Laboratory           *
 *                      Roznov pod Radhostem, Czech Republic           *
 *      Security:       Confidential Proprietary                       *
 *                                                                     *
 * =================================================================== *
 * Copyright (c):      MOTOROLA Inc.,1999, All rights reserved.        *
 *                                                                     *
 * =================================================================== *
 * THIS SOFTWARE IS PROVIDED BY MOTOROLA RSAL "AS IS" AND ANY          *
 * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR  *
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL MOTOROLA RSAL OR         *
 * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    *
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT        *
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;        *
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)            *
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, *
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)       *
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED *
 * OF THE POSSIBILITY OF SUCH DAMAGE.                                  *
 * =================================================================== *
 *
 * HEADER_END
 */


/*      PORTS section           
 */
#define PORTA   (*(volatile char*)(0x00))  /* port A */ 
#define PORTB   (*(volatile char*)(0x01))       /* port B */
#define PORTC   (*(volatile char*)(0x02))       /* port C */
#define PORTD   (*(volatile char*)(0x03))       /* port D */
#define DDRA    (*(char*)(0x04))                /* data direction port A */
#define DDRB    (*(char*)(0x05))                /* data direction port B */
#define DDRC    (*(char*)(0x06))                /* data direction port C */
#define DDRD    (*(char*)(0x07))                /* data direction port D */
#define PORTE   (*(volatile char*)(0x08))  /* port E */
#define PORTF	 (*(volatile char*)(0x09))       /* port F */

#define DDRE    (*(char*)(0x0C))                /* data direction port E */
#define DDRF    (*(char*)(0x0D))                /* data direction port F */

/*      A TIMER section
 */
#define TASC    (*(volatile char*)(0x0E))       /* timer A status/ctrl register */
#define TACNT   (*(volatile int*)(0x0F))        /* timer A counter register */
#define TACNTH  (*(volatile char*)(0x0F)        /* timer A counter high */
#define TACNTL  (*(volatile char*)(0x10))       /* timer A counter low */
#define TAMOD   (*(volatile int*)(0x11))        /* timer A modulo register */
#define TAMODH  (*(volatile char*)(0x11))       /* timer A modulo high */
#define TAMODL  (*(volatile char*)(0x12))       /* timer A modulo low */
#define TASC0   (*(volatile char*)(0x13))  /* timer A channel 0 status/ctrl */
#define TACH0   (*(volatile int*)(0x14))        /* timer A channel 0 register */
#define TACH0H  (*(volatile char*)(0x14))       /* timer A channel 0 high */
#define TACH0L  (*(volatile char*)(0x15))       /* timer A channel 0 low */
#define TASC1   (*(volatile char*)(0x16))       /* timer A channel 1 status/ctrl */
#define TACH1   (*(volatile int*)(0x17))        /* timer A channel 1 register */
#define TACH1H  (*(volatile char*)(0x17))       /* timer A channel 1 high */
#define TACH1L  (*(volatile char*)(0x18))       /* timer A channel 1 low */
#define TASC2   (*(volatile char*)(0x19))  /* timer A channel 2 status/ctrl */
#define TACH2   (*(volatile int*)(0x1A))        /* timer A channel 2 register */
#define TACH2H  (*(volatile char*)(0x1A))       /* timer A channel 2 high */
#define TACH2L  (*(volatile char*)(0x1B))       /* timer A channel 2 low */
#define TASC3   (*(volatile char*)(0x1C))  /* timer A channel 3 status/ctrl */
#define TACH3   (*(volatile int*)(0x1D))        /* timer A channel 3 register */
#define TACH3H  (*(volatile char*)(0x1D))       /* timer A channel 3 high */
#define TACH3L  (*(volatile char*)(0x1E))       /* timer A channel 3 low */

/*      OPTION section
 */
#define MOR     (*(char*)(0x1F))                /* CONFIG Configuration Write-Once Register */

/*      PWM section
*/
#define PCTL1   (*(char*)(0x20))           /* PWM control register 1 */			
#define PCTL2   (*(char*)(0x21))                /* PWM control register 2 */
			
#define FCR     (*(char*)(0x22))	         /* Fault control register */			
#define FSR     (*(volatile char*)(0x23))       /* Fault Status register */			
#define FTAC    (*(char*)(0x24))                /* Fault acknowledge register */			

#define PWMOUT  (*(char*)(0x25))          /* PWM output control register */			
#define PCNT    (*(volatile int*)(0x26))        /* PWM counter register */			
#define PCNTH   (*(volatile char*)(0x26))       /* PWM counter register high */			
#define PCNTL   (*(volatile char*)(0x27))       /* PWM counter register low */			
#define PMOD    (*(volatile int*)(0x28))        /* PWM counter Modulo register */			
#define PMODH   (*(volatile char*)(0x28))       /* PWM counter Modulo register high */			
#define PMODL   (*(volatile char*)(0x29))       /* PWM counter Modulo register low */			
#define PVAL1   (*(volatile int*)(0x2a))        /* PWM 1 value register */			
#define PVAL1H  (*(volatile char*)(0x2a)) /* PWM 1 value register high */			
#define PVAL1L  (*(volatile char*)(0x2b))       /* PWM 1 value register low */			
#define PVAL2   (*(volatile int*)(0x2c))        /* PWM 2 value register */			
#define PVAL2H  (*(volatile char*)(0x2c)) /* PWM 2 value register high */			
#define PVAL2L  (*(volatile char*)(0x2d))       /* PWM 2 value register low */			
#define PVAL3   (*(volatile int*)(0x2e))        /* PWM 3 value register */			
#define PVAL3H  (*(volatile char*)(0x2e)) /* PWM 3 value register high */			
#define PVAL3L  (*(volatile char*)(0x2f))       /* PWM 3 value register low */			
#define PVAL4   (*(volatile int*)(0x30))        /* PWM 4 value register */			
#define PVAL4H  (*(volatile char*)(0x30)) /* PWM 4 value register high */			
#define PVAL4L  (*(volatile char*)(0x31))       /* PWM 4 value register low */			
#define PVAL5   (*(volatile int*)(0x32))        /* PWM 5 value register */			
#define PVAL5H  (*(volatile char*)(0x32)) /* PWM 5 value register high */			
#define PVAL5L  (*(volatile char*)(0x33))	 /* PWM 5 value register low */			
#define PVAL6   (*(volatile int*)(0x34))        /* PWM 6 value register */			
#define PVAL6H  (*(volatile char*)(0x34)) /* PWM 6 value register high */			
#define PVAL6L  (*(volatile char*)(0x35))       /* PWM 6 value register low */			

#define DEADTM  (*(volatile char*)(0x36))       /* Dead Time Write-once register */
#define DISMAP  (*(volatile char*)(0x37))       /* PWM Disable Mapping Write-once register */

/*      SCI section
 */
#define SCC1    (*(char*)(0x38))	         /* SCI control register 1 */
#define SCC2    (*(char*)(0x39))                /* SCI control register 2 */
#define SCC3    (*(char*)(0x3A))                /* SCI control register 3 */
#define SCS1    (*(volatile char*)(0x3B))       /* SCI status register 1 */
#define SCS2    (*(volatile char*)(0x3C))       /* SCI status register 2 */
#define SCDR    (*(volatile char*)(0x3D))       /* SCI data register */
#define SCBR    (*(char*)(0x3E))                /* SCI baud rate */

/*      INTERRUPT section
 */
#define ISCR    (*(volatile char*)(0x3F))       /* IRQ status/control register */

/*      A/D section
 */
#define ADSCR   (*(volatile char*)(0x40))  /* ADC status and control register */
#define ADR     (*(volatile int*)(0x41))        /* ADC data register */
#define ADRH    (*(volatile char*)(0x41))       /* ADC data register high */
#define ADRL    (*(volatile char*)(0x42))       /* ADC data register low */
#define ADCLK   (*(char*)(0x43))                /* ADC clock register */
										
/*      SPI section
 */
#define SPCR    (*(char*)(0x44))                /* SPI control register */
#define SPSCR   (*(volatile char*)(0x45))       /* SPI control/status register */
#define SPDR    (*(volatile char*)(0x46))       /* SPI data register */

/*      B TIMER section
 */
#define TBSC    (*(volatile char*)(0x51))       /* timer B status/ctrl register */
#define TBCNT   (*(volatile int*)(0x52))        /* timer B counter register */
#define TBCNTH  (*(volatile char*)(0x52))       /* timer B counter high */
#define TBCNTL  (*(volatile char*)(0x53))       /* timer B counter low */
#define TBMOD   (*(volatile int*)(0x54))        /* timer B modulo register */
#define TBMODH  (*(volatile char*)(0x54)        /* timer B modulo high */
#define TBMODL  (*(volatile char*)(0x55))       /* timer B modulo low */
#define TBSC0   (*(volatile char*)(0x56))       /* timer B channel 0 status/ctrl */
#define TBCH0   (*(volatile int*)(0x57))        /* timer B channel 0 register */
#define TBCH0H  (*(volatile char*)(0x57))       /* timer B channel 0 high */
#define TBCH0L  (*(volatile char*)(0x58))       /* timer B channel 0 low */
#define TBSC1   (*(volatile char*)(0x59))       /* timer B channel 1 status/ctrl */
#define TBCH1   (*(volatile int*)(0x5A))        /* timer B channel 1 register */
#define TBCH1H  (*(volatile char*)(0x5A))       /* timer B channel 1 high */
#define TBCH1L  (*(volatile char*)(0x5B))       /* timer B channel 1 low */

/*      PLL section
 */
#define PCTL   (*(volatile char*)(0x5C))    /* PLL control register */
#define PBWC   (*(volatile char*)(0x5D))    /* PLL bandwidth register */
#define PPG    (*(char*)(0x5E))                 /* PLL programming register */

/*      SIM section
 */
#define SBSR    (*(volatile char*)(0xFE00))     /* SIM break status register */
#define SRSR    (*(volatile char*)(0xFE01))     /* SIM reset status register */
#define SBFCR   (*(char*)(0xFE03))              /* SIM break control register */
#define FLCR    (*(char*)(0xFE08))              /* FLASH control register */


#define LVISCR (*(volatile char*)(0xFE0f))      /* LVI status/control register */
#define FLBPR  (*(volatile char*)(0xFF80))      /* FLASH block protect register */
#define COPCTL (*(volatile char*)(0xFFFF))      /* COP control register */