sst29xe020.txt

SST 系列Nor flash 的读写源码

             /************************************************************************************/
             /*                                      WRITTEN OPERATION	                         */
             /*	                                                                                 */
             /* Issue the 3-byte "enable protection" sequence followed by 128 bytes	         */
             /* of data written to the 29EE020.	                                                 */
             /************************************************************************************/

             Temp =  (BYTE far *)0xC0005555;                      /* set up address to be C000:555h	*/
              *Temp = 0xAA;                                       /* write data 0xAA to the address	*/
             Temp =  (BYTE far *)0xC0002AAA;                      /* set up address to be C000:2AAAh	*/
              *Temp = 0x55;                                       /* write data 0x55 to the address	*/
             Temp =  (BYTE far *)0xC0005555;                      /* set up address to be C000:5555h	*/
              *Temp = 0xA0;                                       /* write data 0xA0 to the address	*/

              for (Index = 0; Index < ROW_SIZE; Index++)
              {
                            *DestBuf++ = *SourceBuf++;     /* transfer data from source to destination */

              }
   	      Delay_1_Milli_Second();           /* wait 1ms to start writing	         */
             
              Check_Toggle_Ready(Dst);          /* wait for TOGGLE bit to get ready	 */
}




/******************************************************************************************************/
/* PROCEDURE:	 Check_Toggle_Ready	                                                              */
/*			                                                                              */
/* During the internal write cycle, any consecutive read operation	                              */
/* on DQ6 will produce alternating 0抯 and 1抯 i.e. toggling between	                              */
/* 0 and 1. When the write cycle is completed, DQ6 of the data will	                              */
/* stop toggling. After the DQ6 data bit stops toggling, the device is ready	                      */
/* for next operation.	                                                                              */
/*			                                                                              */
/* Input:		                                                                              */
/*           Dst	must already set-up by the caller	                                      */
/*			                                                                              */
/* Output:		                                                                              */
/*           None		                                                                      */
/******************************************************************************************************/

void Check_Toggle_Ready (BYTE far  *Dst)
{
	BYTE Loop = TRUE;
	BYTE PreData;
	BYTE CurrData;
	unsigned long TimeOut = 0;

	PreData = *Dst;
	PreData = PreData & 0x40;
	while ((TimeOut< 0x07FFFFFF) && (Loop))
	{
		CurrData = *Dst;
		CurrData = CurrData & 0x40;
		if (PreData == CurrData)
  	Loop = FALSE;                /* ready to exit the while loop */
		PreData = CurrData;
		TimeOut++;
	}
}




/******************************************************************************************************/
/* PROCEDURE: 	Check_Data_Polling	                                                              */
/*			                                                                              */
/* During the internal write cycle, any attempt to read DQ7 of the last byte loaded during	      */
/* the page/byte-load cycle will receive the complement of the true data.  Once the	              */
/* write cycle is completed, DQ7 will show true data.	                                              */
/*			                                                                              */
/* Input:		                                                                              */
/*           Dst	must already set-up by the caller	                                      */
/*           True	Datathis is the original (true) data	                                      */      
/*			                                                                              */
/* Output:		                                                                              */
/*           None		                                                                      */
/******************************************************************************************************/

void Check_Data_Polling (BYTE far  *Dst,       BYTE TrueData)
{
	BYTE Loop = TRUE;
	BYTE CurrData;
	unsigned long TimeOut = 0;

	TrueData = TrueData &  0x80;
	while ((TimeOut< 0x07FFFFFF) && (Loop))
	{
		CurrData = *Dst;
		CurrData = CurrData & 0x80;
		if (TrueData == CurrData)			
Loop = FALSE;                           /* ready to exit the while loop  */
		TimeOut++;
	}
}





/******************************************************************************************************/
/* PROCEDURE: 	Enable_Chip_Data_Protection							      */
/*												      */
/* This procedure ENABLES the data  protection feature on the 29EE020				      */
/* 2 Mbit Page Mode EEPROM.  After calling this routine, the chip cannot be written		      */
/* unless preceded by the three Byte-Load sequence.						      */
/*												      */
/* Input:								   			      */
/*           None										      */
/*									                     	      */
/* Output:								          		      */
/*           None										      */
/******************************************************************************************************/

void Enable_Chip_Data_Protection()
{
	BYTE  far  *Temp;

	Temp  = (BYTE far *)0xC0005555;			/* set up address to be C000:5555h	*/
	*Temp = 0xAA;					/* write data 0xAA to the address	*/
	Temp  = (BYTE far *)0xC0002AAA;			/* set up address to be C000:2AAAh	*/
	*Temp = 0x55;					/* write data 0x55 to the address	*/
	Temp  = (BYTE far *)0xC0005555;			/* set up address to be C000:5555h	*/
	*Temp = 0xA0;					/* write data 0xA0 to the address	*/

	Delay_10_Milli_Second();
}
8086 ASSEMBLY LANGUAGE DRIVERS

; ====================================================================
; Copyright Silicon Storage Technology, Inc. (SST), 1994-1997
; EXAMPLE 8086 assembly Drivers for 29EE020 2 Mbit Page Mode EEPROM
; Chi Chung Yin,  Silicon Storage Technology
;
; Revision 2.0, April 8, 1997
;
; This file requires these external "timing" routines:
;
;	1.)  Delay_1_Milli_Second
;	2.)  Delay_10_Milli_ Second
;	3.)  Delay_10_Micro_Second
; ====================================================================

ROW_SIZE		EQU	128			;Must be 128 bytes for 29EE020

SST_ID			EQU	0BFh			;SST Manufacturer抯 ID code
SST_29EE020		EQU	010h			;SST 29EE020 internal code
							;NOTE-Use "012h" for 29LE020 and 
29VE020

ABS_SEGMENT	EQU	0C000h

extrn	Delay_1_Milli_Second:near
extrn	Delay_10_Milli_Second:near
extrn	Delay_10_Micro_Second:near





;=======================================================================
; PROCEDURE:			Check_SST_29EE020
;
; This procedure decides whether a physical hardware device has a SST抯
; 29EE020 2 Mbit Page Mode EEPROM installed or not.
;
; Input:
;	None
;
; Output:
; 	carry bit:   SET means not a SST 29EE020
;	carry bit:   CLEARED means a SST 29EE020
;
;=======================================================================

Check_SST_29EE020	proc 	near

	push 	ax				; preserve registers