📄 fet140_ta_pwm04.s43
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#include "msp430x14x.h"
;******************************************************************************
; MSP-FET430P140 Demo - Timer_A PWM TA1-2 up-downmode, DCO SMCLK
;
; Description; This program will generate a two PWM outputs on P1.2/1.3 using
; Timer_A in an upmode. The value in CCR0, 128, defines the period/2 and the
; values in CCR1 and CCR1 the duty PWM cycles. Using ~ 800kHz SMCLK as TACLK,
; the timer period is ~ 320us with a 75% duty cycle on P1.2 and 25% on P1.3.
; SMCLK = MCLK = TACLK = default DCO ~ 800kHz.
; As coded, the output signals TA1 on P1.2 and TA2 on P1.3 are inverted.
;
; MSP430F149
; -----------------
; /|\| XIN|-
; | | |
; --|RST XOUT|-
; | |
; | P1.2|--> CCR1 - 75% PWM
; | P1.3|--> CCR2 - 25% PWM
;
; M.Buccini
; Texas Instruments, Inc
; January 2002
;******************************************************************************
;-----------------------------------------------------------------------------
ORG 01100h ; Program Start
;-----------------------------------------------------------------------------
RESET mov.w #0A00h,SP ; Initialize 'F149 stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupTA mov.w #TASSEL1+TACLR,&TACTL ; SMCLK, Clear TAR
SetupC0 mov.w #128,&CCR0 ; PWM Period/2
SetupC1 mov.w #OUTMOD_2,&CCTL1 ; CCR1 toggle/reset
mov.w #64,&CCR1 ; CCR1 PWM Duty Cycle
SetupC2 mov.w #OUTMOD_6,&CCTL2 ; CCR2 toggle/set
mov.w #96,&CCR2 ; CCR2 PWM duty cycle
SetupP1 bis.b #00Ch,&P1DIR ; P1.2 and P1.3 output
bis.b #00Ch,&P1SEL ; P1.2 and P1.3 TA1/2 otions
bis.w #MC1+MC0,&TACTL ; Start Timer_A in up-down mode
;
Mainloop bis.w #CPUOFF,SR ; CPU off
nop ; Required only for C-spy
;
;------------------------------------------------------------------------------
; Interrupt Vectors Used MSP430x13x/14x
;------------------------------------------------------------------------------
ORG 0FFFEh ; MSP430 RESET Vector
DW RESET ;
END
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