fet140_tb09.s43

TI低功耗MCU用例子

#include  "msp430x14x.h"
;******************************************************************************
;   MSP-FET430P140 Demo - Timer_B Toggle P4.0-6 CCRx Contmode ISR, XT2 SMCLK 
;
;   Description; Use timer_A CCRx units and overflow to generate four
;   independent timing intervals. For demonstration, CCR0, CCR1 and CCR2 output
;   units are optionally selected with port pins P1.1, P1.2 and P1.3 in toggle
;   mode. As such, these pins will toggle when respective CCRx registers match
;   the TAR counter. Interrupts are also enabled enabled with all CCRx units,
;   software loads offset to next inderval only - as long as the interval offset
;   is aded to CCRx, toggle rate is generated in hardware. Timer_A overflow ISR 
;   is used to toggle P1.0 with software. 
;   MCLK = SMCLK = TACLK = XT2 = HF XTAL
;   As coded with TACLK = HF XTAL and assuming HF XTAL = 8Mhz, toggle rates:
;   P4.0 = TBCCR0 = 8MHz/(2*200) = 20kHz
;   P4.1 = TBCCR1 = 8MHz/(2*400) = 10kHz
;   P4.2 = TBCCR2 = 8MHz/(2*500) = 8000Hz
;   P4.3 = TBCCR3 = 8MHz/(2*1000) = 4000Hz
;   P4.4 = TBCCR4 = 8MHz/(2*2000) = 2000Hz
;   P4.5 = TBCCR5 = 8MHz/(2*4000) = 1000Hz
;   P4.6 = TBCCR6 = 8MHz/(2*10000) = 400Hz
;   P1.0 = overflow = 8MHz/(2*65536) = 61Hz
;   Proper use of TAIV interrupt vector generator demonstrated.   
;   //** HF XTAL NOT INSTALLED ON FET **//;
;
;                MSP430F149
;             -----------------
;         /|\|            XT2IN|-  
;          | |                 | 8Mhz
;          --|RST        XT2OUT|-
;            |                 |
;            |             P4.0|--> TBCCR0
;            |             P4.1|--> TBCCR1
;            |             P4.2|--> TBCCR2
;            |             P4.3|--> TBCCR3
;            |             P4.4|--> TBCCR4
;            |             P4.5|--> TBCCR5
;            |             P4.6|--> TBCCR6
;            |             P1.0|--> overflow/software
;
;   M.Buccini
;   Texas Instruments, Inc
;   January 2002
;******************************************************************************
;------------------------------------------------------------------------------ 
            ORG     01100h                  ; Program Start
;------------------------------------------------------------------------------ 
RESET       mov.w   #0A00h,SP               ; Initialize 'F149 stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupBC     bic.b   #XT2OFF,&BCSCTL1        ; XT2 = HF XTAL
SetupOsc    bic.b   #OFIFG,&IFG1            ; Clear OSC fault flag 
            mov.w   #0FFh,R15               ; R15 = Delay 
SetupOsc1   dec.w   R15                     ; Additional delay to ensure start 
            jnz     SetupOsc1               ;
            bit.b   #OFIFG,&IFG1            ; OSC fault flag set? 
            jnz     SetupOsc                ; OSC Fault, clear flag again 
            bis.b   #SELM1+SELS,&BCSCTL2    ; MCLK = SMCLK = XT2
SetupTB     mov.w   #TBSSEL1+TBCLR+TBIE,&TBCTL   ; SMCLK, clear TAB, interrupt
SetupCx     mov.w   #OUTMOD_4+CCIE,&TBCCTL0 ; TBCCR0 interrupt enabled
            mov.w   #OUTMOD_4+CCIE,&TBCCTL1 ; TBCCR1 interrupt enabled
            mov.w   #OUTMOD_4+CCIE,&TBCCTL2 ; TBCCR2 interrupt enabled
            mov.w   #OUTMOD_4+CCIE,&TBCCTL3 ; TBCCR3 interrupt enabled
            mov.w   #OUTMOD_4+CCIE,&TBCCTL4 ; TBCCR4 interrupt enabled
            mov.w   #OUTMOD_4+CCIE,&TBCCTL5 ; TBCCR5 interrupt enabled
            mov.w   #OUTMOD_4+CCIE,&TBCCTL6 ; TBCCR6 interrupt enabled
            mov.w   #200,&TBCCR0            ; 
            mov.w   #400,&TBCCR1            ; 
            mov.w   #500,&TBCCR2            ; 
            mov.w   #1000,&TBCCR3           ; 
            mov.w   #2000,&TBCCR4           ; 
            mov.w   #4000,&TBCCR5           ; 
            mov.w   #10000,&TBCCR6          ; 
SetupP4     bis.b   #07Fh,&P4SEL            ; P4.x - P4.6 option select
            bis.b   #07Fh,&P4DIR            ; P4.x = outputs 
SetupP1     bis.b   #001h,&P1DIR            ; P1.0 = output 
            bis.w   #MC1,&TBCTL             ; Start Timer_B in continous mode
            eint                            ; Enable interrupts
                                            ;													  
Mainloop    bis.w   #CPUOFF,SR              ; Enter LPM3
            nop                             ; Required for C-spy
                                            ;
;------------------------------------------------------------------------------ 
TB0_ISR;    Toggle P1.0
;------------------------------------------------------------------------------ 
            add.w   #200,&TBCCR0              ; Offset until next interrupt
            reti                            ;		 
;
;------------------------------------------------------------------------------ 
TBX_ISR;    Common ISR for TBCCR1-6 and overflow
;------------------------------------------------------------------------------ 
            add.w   &TBIV,PC                ; Add Timer_B offset vector
            reti                            ; CCR0 - no source
            jmp     TBCCR1_ISR              ; TBCCR1
            jmp     TBCCR2_ISR              ; TBCCR2
            jmp     TBCCR3_ISR              ; TBCCR3
            jmp     TBCCR4_ISR              ; TBCCR4
            jmp     TBCCR5_ISR              ; TBCCR5
            jmp     TBCCR6_ISR              ; TBCCR6
TB_over     xor.b   #001h,&P1OUT            ; Toggle P1.0
            reti                            ; Return from overflow ISR		 
                                            ;
TBCCR1_ISR  add.w   #400,&TBCCR1            ; Offset until next interrupt
            jmp     TBX_ISR                 ;
            reti                            ; Return ISR		 
                                            ;            
TBCCR2_ISR  add.w   #500,&TBCCR2            ; Offset until next interrupt
            jmp     TBX_ISR                 ;
            reti                            ; Return ISR		 
                                            ;
TBCCR3_ISR  add.w   #1000,&TBCCR3           ; Offset until next interrupt
            jmp     TBX_ISR                 ;
            reti                            ; Return ISR		 
                                            ;
TBCCR4_ISR  add.w   #2000,&TBCCR4           ; Offset until next interrupt
            jmp     TBX_ISR                 ;
            reti                            ; Return ISR		 
                                            ;            
TBCCR5_ISR  add.w   #4000,&TBCCR5           ; Offset until next interrupt
            jmp     TBX_ISR                 ;
            reti                            ; Return ISR		 
                                            ;
TBCCR6_ISR  add.w   #10000,&TBCCR6          ; Offset until next interrupt
            jmp     TBX_ISR                 ;
            reti                            ; Return ISR		 
                                            ;
;------------------------------------------------------------------------------ 
;           Interrupt Vectors Used MSP430x13x/14x          
;------------------------------------------------------------------------------ 
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ; 
            ORG     0FFFAh                  ; Timer_B0 Vector
            DW      TB0_ISR                 ; 
            ORG     0FFF8h                  ; Timer_BX Vector
            DW      TBX_ISR                 ; 
            END