tft.fit.qmsg

stm32数码相框

{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" {  } {  } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.631 ns register register " "Info: Estimated most critical path is register to register delay of 8.631 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|temp2\[5\] 1 REG LAB_X6_Y4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y4; Fanout = 4; REG Node = 'lcd:inst\|temp2\[5\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|temp2[5] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 275 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.914 ns) 1.835 ns lcd:inst\|Equal4~1 2 COMB LAB_X5_Y4 1 " "Info: 2: + IC(0.921 ns) + CELL(0.914 ns) = 1.835 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'lcd:inst\|Equal4~1'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.835 ns" { lcd:inst|temp2[5] lcd:inst|Equal4~1 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 220 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.059 ns) + CELL(0.200 ns) 3.094 ns lcd:inst\|Equal4~2 3 COMB LAB_X5_Y4 2 " "Info: 3: + IC(1.059 ns) + CELL(0.200 ns) = 3.094 ns; Loc. = LAB_X5_Y4; Fanout = 2; COMB Node = 'lcd:inst\|Equal4~2'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { lcd:inst|Equal4~1 lcd:inst|Equal4~2 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 220 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.200 ns) 4.277 ns lcd:inst\|ADDER_CON\[17\]~36 4 COMB LAB_X5_Y4 18 " "Info: 4: + IC(0.983 ns) + CELL(0.200 ns) = 4.277 ns; Loc. = LAB_X5_Y4; Fanout = 18; COMB Node = 'lcd:inst\|ADDER_CON\[17\]~36'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { lcd:inst|Equal4~2 lcd:inst|ADDER_CON[17]~36 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.111 ns) + CELL(1.243 ns) 8.631 ns lcd:inst\|ADDER_CON\[17\] 5 REG LAB_X12_Y1 2 " "Info: 5: + IC(3.111 ns) + CELL(1.243 ns) = 8.631 ns; Loc. = LAB_X12_Y1; Fanout = 2; REG Node = 'lcd:inst\|ADDER_CON\[17\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "4.354 ns" { lcd:inst|ADDER_CON[17]~36 lcd:inst|ADDER_CON[17] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.557 ns ( 29.63 % ) " "Info: Total cell delay = 2.557 ns ( 29.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.074 ns ( 70.37 % ) " "Info: Total interconnect delay = 6.074 ns ( 70.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "8.631 ns" { lcd:inst|temp2[5] lcd:inst|Equal4~1 lcd:inst|Equal4~2 lcd:inst|ADDER_CON[17]~36 lcd:inst|ADDER_CON[17] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "29 " "Info: Average interconnect usage is 29% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "29 X0_Y0 X13_Y8 " "Info: Peak interconnect usage is 29% of the available device resources in the region that extends from location X0_Y0 to location X13_Y8" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/570/570_h_speed/TFT.fit.smsg " "Info: Generated suppressed messages file F:/570/570_h_speed/TFT.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "187 " "Info: Peak virtual memory: 187 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 12 20:45:45 2011 " "Info: Processing ended: Wed Jan 12 20:45:45 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}