prev_cmp_tft.qmsg

stm32数码相框

{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Peak virtual memory: 145 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 12 17:36:30 2011 " "Info: Processing ended: Wed Jan 12 17:36:30 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version " "Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 12 17:36:32 2011 " "Info: Processing started: Wed Jan 12 17:36:32 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off TFT -c TFT " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off TFT -c TFT" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } } { "c:/electron/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/electron/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|HSYNC " "Info: Detected ripple clock \"lcd:inst\|HSYNC\" as buffer" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } } { "c:/electron/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/electron/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|HSYNC" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|CLKOUT " "Info: Detected ripple clock \"lcd:inst\|CLKOUT\" as buffer" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } } { "c:/electron/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/electron/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|CLKOUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register lcd:inst\|temp2\[5\] register lcd:inst\|ADDER_TFT\[8\] 46.74 MHz 21.397 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 46.74 MHz between source register \"lcd:inst\|temp2\[5\]\" and destination register \"lcd:inst\|ADDER_TFT\[8\]\" (period= 21.397 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.198 ns + Longest register register " "Info: + Longest register to register delay is 9.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|temp2\[5\] 1 REG LC_X7_Y6_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y6_N3; Fanout = 4; REG Node = 'lcd:inst\|temp2\[5\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|temp2[5] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 285 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.881 ns) + CELL(0.740 ns) 2.621 ns lcd:inst\|Equal4~1 2 COMB LC_X10_Y6_N0 1 " "Info: 2: + IC(1.881 ns) + CELL(0.740 ns) = 2.621 ns; Loc. = LC_X10_Y6_N0; Fanout = 1; COMB Node = 'lcd:inst\|Equal4~1'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.621 ns" { lcd:inst|temp2[5] lcd:inst|Equal4~1 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 216 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.734 ns) + CELL(0.740 ns) 4.095 ns lcd:inst\|Equal4~2 3 COMB LC_X10_Y6_N7 2 " "Info: 3: + IC(0.734 ns) + CELL(0.740 ns) = 4.095 ns; Loc. = LC_X10_Y6_N7; Fanout = 2; COMB Node = 'lcd:inst\|Equal4~2'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.474 ns" { lcd:inst|Equal4~1 lcd:inst|Equal4~2 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 216 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.791 ns) + CELL(0.511 ns) 5.397 ns lcd:inst\|ADDER_TFT\[17\]~36 4 COMB LC_X10_Y6_N3 18 " "Info: 4: + IC(0.791 ns) + CELL(0.511 ns) = 5.397 ns; Loc. = LC_X10_Y6_N3; Fanout = 18; COMB Node = 'lcd:inst\|ADDER_TFT\[17\]~36'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.302 ns" { lcd:inst|Equal4~2 lcd:inst|ADDER_TFT[17]~36 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.558 ns) + CELL(1.243 ns) 9.198 ns lcd:inst\|ADDER_TFT\[8\] 5 REG LC_X11_Y2_N9 3 " "Info: 5: + IC(2.558 ns) + CELL(1.243 ns) = 9.198 ns; Loc. = LC_X11_Y2_N9; Fanout = 3; REG Node = 'lcd:inst\|ADDER_TFT\[8\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.801 ns" { lcd:inst|ADDER_TFT[17]~36 lcd:inst|ADDER_TFT[8] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.234 ns ( 35.16 % ) " "Info: Total cell delay = 3.234 ns ( 35.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.964 ns ( 64.84 % ) " "Info: Total interconnect delay = 5.964 ns ( 64.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "9.198 ns" { lcd:inst|temp2[5] lcd:inst|Equal4~1 lcd:inst|Equal4~2 lcd:inst|ADDER_TFT[17]~36 lcd:inst|ADDER_TFT[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "9.198 ns" { lcd:inst|temp2[5] {} lcd:inst|Equal4~1 {} lcd:inst|Equal4~2 {} lcd:inst|ADDER_TFT[17]~36 {} lcd:inst|ADDER_TFT[8] {} } { 0.000ns 1.881ns 0.734ns 0.791ns 2.558ns } { 0.000ns 0.740ns 0.740ns 0.511ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-11.490 ns - Smallest " "Info: - Smallest clock skew is -11.490 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns lcd:inst\|ADDER_TFT\[8\] 2 REG LC_X11_Y2_N9 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X11_Y2_N9; Fanout = 3; REG Node = 'lcd:inst\|ADDER_TFT\[8\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clkin lcd:inst|ADDER_TFT[8] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|ADDER_TFT[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|ADDER_TFT[8] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 15.171 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 15.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns lcd:inst\|CLKOUT 2 REG LC_X11_Y4_N6 16 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X11_Y4_N6; Fanout = 16; REG Node = 'lcd:inst\|CLKOUT'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clkin lcd:inst|CLKOUT } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.247 ns) + CELL(1.294 ns) 9.598 ns lcd:inst\|HSYNC 3 REG LC_X10_Y4_N5 18 " "Info: 3: + IC(4.247 ns) + CELL(1.294 ns) = 9.598 ns; Loc. = LC_X10_Y4_N5; Fanout = 18; REG Node = 'lcd:inst\|HSYNC'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.541 ns" { lcd:inst|CLKOUT lcd:inst|HSYNC } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.655 ns) + CELL(0.918 ns) 15.171 ns lcd:inst\|temp2\[5\] 4 REG LC_X7_Y6_N3 4 " "Info: 4: + IC(4.655 ns) + CELL(0.918 ns) = 15.171 ns; Loc. = LC_X7_Y6_N3; Fanout = 4; REG Node = 'lcd:inst\|temp2\[5\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.573 ns" { lcd:inst|HSYNC lcd:inst|temp2[5] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 285 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 30.78 % ) " "Info: Total cell delay = 4.669 ns ( 30.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.502 ns ( 69.22 % ) " "Info: Total interconnect delay = 10.502 ns ( 69.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "15.171 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[5] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "15.171 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[5] {} } { 0.000ns 0.000ns 1.600ns 4.247ns 4.655ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|ADDER_TFT[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|ADDER_TFT[8] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "15.171 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[5] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "15.171 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[5] {} } { 0.000ns 0.000ns 1.600ns 4.247ns 4.655ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 285 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "9.198 ns" { lcd:inst|temp2[5] lcd:inst|Equal4~1 lcd:inst|Equal4~2 lcd:inst|ADDER_TFT[17]~36 lcd:inst|ADDER_TFT[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "9.198 ns" { lcd:inst|temp2[5] {} lcd:inst|Equal4~1 {} lcd:inst|Equal4~2 {} lcd:inst|ADDER_TFT[17]~36 {} lcd:inst|ADDER_TFT[8] {} } { 0.000ns 1.881ns 0.734ns 0.791ns 2.558ns } { 0.000ns 0.740ns 0.740ns 0.511ns 1.243ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|ADDER_TFT[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|ADDER_TFT[8] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "15.171 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[5] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "15.171 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[5] {} } { 0.000ns 0.000ns 1.600ns 4.247ns 4.655ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clkin 30 " "Warning: Circuit may not operate. Detected 30 non-operational path(s) clocked by clock \"clkin\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lcd:inst\|delay lcd:inst\|temp2\[0\] clkin 6.707 ns " "Info: Found hold time violation between source  pin or register \"lcd:inst\|delay\" and destination pin or register \"lcd:inst\|temp2\[0\]\" for clock \"clkin\" (Hold time is 6.707 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "11.490 ns + Largest " "Info: + Largest clock skew is 11.490 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 15.171 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 15.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns lcd:inst\|CLKOUT 2 REG LC_X11_Y4_N6 16 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X11_Y4_N6; Fanout = 16; REG Node = 'lcd:inst\|CLKOUT'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clkin lcd:inst|CLKOUT } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.247 ns) + CELL(1.294 ns) 9.598 ns lcd:inst\|HSYNC 3 REG LC_X10_Y4_N5 18 " "Info: 3: + IC(4.247 ns) + CELL(1.294 ns) = 9.598 ns; Loc. = LC_X10_Y4_N5; Fanout = 18; REG Node = 'lcd:inst\|HSYNC'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.541 ns" { lcd:inst|CLKOUT lcd:inst|HSYNC } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.655 ns) + CELL(0.918 ns) 15.171 ns lcd:inst\|temp2\[0\] 4 REG LC_X7_Y6_N6 4 " "Info: 4: + IC(4.655 ns) + CELL(0.918 ns) = 15.171 ns; Loc. = LC_X7_Y6_N6; Fanout = 4; REG Node = 'lcd:inst\|temp2\[0\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.573 ns" { lcd:inst|HSYNC lcd:inst|temp2[0] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 285 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 30.78 % ) " "Info: Total cell delay = 4.669 ns ( 30.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.502 ns ( 69.22 % ) " "Info: Total interconnect delay = 10.502 ns ( 69.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "15.171 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "15.171 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[0] {} } { 0.000ns 0.000ns 1.600ns 4.247ns 4.655ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns lcd:inst\|delay 2 REG LC_X1_Y4_N8 46 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y4_N8; Fanout = 46; REG Node = 'lcd:inst\|delay'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clkin lcd:inst|delay } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|delay } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|delay {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "15.171 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "15.171 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[0] {} } { 0.000ns 0.000ns 1.600ns 4.247ns 4.655ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|delay } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|delay {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.628 ns - Shortest register register " "Info: - Shortest register to register delay is 4.628 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|delay 1 REG LC_X1_Y4_N8 46 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N8; Fanout = 46; REG Node = 'lcd:inst\|delay'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|delay } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.385 ns) + CELL(1.243 ns) 4.628 ns lcd:inst\|temp2\[0\] 2 REG LC_X7_Y6_N6 4 " "Info: 2: + IC(3.385 ns) + CELL(1.243 ns) = 4.628 ns; Loc. = LC_X7_Y6_N6; Fanout = 4; REG Node = 'lcd:inst\|temp2\[0\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "4.628 ns" { lcd:inst|delay lcd:inst|temp2[0] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 285 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.243 ns ( 26.86 % ) " "Info: Total cell delay = 1.243 ns ( 26.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.385 ns ( 73.14 % ) " "Info: Total interconnect delay = 3.385 ns ( 73.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "4.628 ns" { lcd:inst|delay lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "4.628 ns" { lcd:inst|delay {} lcd:inst|temp2[0] {} } { 0.000ns 3.385ns } { 0.000ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 285 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "15.171 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "15.171 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[0] {} } { 0.000ns 0.000ns 1.600ns 4.247ns 4.655ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|delay } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|delay {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "4.628 ns" { lcd:inst|delay lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "4.628 ns" { lcd:inst|delay {} lcd:inst|temp2[0] {} } { 0.000ns 3.385ns } { 0.000ns 1.243ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "lcd:inst\|DATA\[13\] sram_data\[13\] clkin 2.257 ns register " "Info: tsu for register \"lcd:inst\|DATA\[13\]\" (data pin = \"sram_data\[13\]\", clock pin = \"clkin\") is 2.257 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.605 ns + Longest pin register " "Info: + Longest pin to register delay is 5.605 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sram_data\[13\] 1 PIN PIN_111 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_111; Fanout = 1; PIN Node = 'sram_data\[13\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { sram_data[13] } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 96 320 498 112 "sram_data\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sram_data~2 2 COMB IOC_X12_Y8_N3 1 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X12_Y8_N3; Fanout = 1; COMB Node = 'sram_data~2'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { sram_data[13] sram_data~2 } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 96 320 498 112 "sram_data\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.412 ns) + CELL(1.061 ns) 5.605 ns lcd:inst\|DATA\[13\] 3 REG LC_X5_Y4_N2 1 " "Info: 3: + IC(3.412 ns) + CELL(1.061 ns) = 5.605 ns; Loc. = LC_X5_Y4_N2; Fanout = 1; REG Node = 'lcd:inst\|DATA\[13\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "4.473 ns" { sram_data~2 lcd:inst|DATA[13] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 39.13 % ) " "Info: Total cell delay = 2.193 ns ( 39.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.412 ns ( 60.87 % ) " "Info: Total interconnect delay = 3.412 ns ( 60.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.605 ns" { sram_data[13] sram_data~2 lcd:inst|DATA[13] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "5.605 ns" { sram_data[13] {} sram_data~2 {} lcd:inst|DATA[13] {} } { 0.000ns 0.000ns 3.412ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns lcd:inst\|DATA\[13\] 2 REG LC_X5_Y4_N2 1 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X5_Y4_N2; Fanout = 1; REG Node = 'lcd:inst\|DATA\[13\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clkin lcd:inst|DATA[13] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_D