📄 prev_cmp_tft.qmsg
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{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} } { } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkin Global clock in PIN 20 " "Info: Automatically promoted signal \"clkin\" to use Global clock in PIN 20" { } { { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } } } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "lcd:inst\|HSYNC Global clock " "Info: Automatically promoted some destinations of signal \"lcd:inst\|HSYNC\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "HSYNC " "Info: Destination \"HSYNC\" may be non-global or may not use global clock" { } { { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 240 320 496 256 "HSYNC" "" } } } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:inst\|HSYNC " "Info: Destination \"lcd:inst\|HSYNC\" may be non-global or may not use global clock" { } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } } } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "lcd:inst\|CLKOUT Global clock " "Info: Automatically promoted some destinations of signal \"lcd:inst\|CLKOUT\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLKOUT " "Info: Destination \"CLKOUT\" may be non-global or may not use global clock" { } { { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 224 320 496 240 "CLKOUT" "" } } } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:inst\|CLKOUT " "Info: Destination \"lcd:inst\|CLKOUT\" may be non-global or may not use global clock" { } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } } } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" { } { } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" { } { } 0 0 "Started processing fast register assignments" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" { } { } 0 0 "Finished processing fast register assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
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