prev_cmp_tft.qmsg

stm32数码相框

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version " "Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 12 17:36:14 2011 " "Info: Processing started: Wed Jan 12 17:36:14 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off TFT -c TFT " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TFT -c TFT" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tft.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file tft.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TFT " "Info: Found entity 1: TFT" {  } { { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "lcd.v(76) " "Warning (10268): Verilog HDL information at lcd.v(76): always construct contains both blocking and non-blocking assignments" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 76 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "lcd.v(89) " "Warning (10268): Verilog HDL information at lcd.v(89): always construct contains both blocking and non-blocking assignments" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 89 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "lcd.v(117) " "Warning (10268): Verilog HDL information at lcd.v(117): always construct contains both blocking and non-blocking assignments" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_test " "Info: Found entity 1: lcd_test" {  } { { "lcd_test.v" "" { Text "F:/570/570_h_speed/lcd_test.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "ADDER packed lcd.v(10) " "Warning (10227): Verilog HDL Port Declaration warning at lcd.v(10): data type declaration for \"ADDER\" declares packed dimensions but the port declaration declaration does not" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 10 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_HDL_SEE_DECLARATION" "ADDER lcd.v(5) " "Info (10499): HDL info at lcd.v(5): see declaration for object \"ADDER\"" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 0 0 } }  } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "TFT " "Info: Elaborating entity \"TFT\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcd:inst " "Info: Elaborating entity \"lcd\" for hierarchy \"lcd:inst\"" {  } { { "TFT.bdf" "inst" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 72 72 296 392 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "TONG lcd.v(8) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(8): object \"TONG\" assigned a value but never read" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 8 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tmp lcd.v(14) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(14): object \"tmp\" assigned a value but never read" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 14 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "temp4 lcd.v(17) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(17): object \"temp4\" assigned a value but never read" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}