prev_cmp_tft.tan.qmsg

stm32数码相框

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register lcd:inst\|temp2\[9\] register lcd:inst\|ADDER_CON\[8\] 51.79 MHz 19.31 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 51.79 MHz between source register \"lcd:inst\|temp2\[9\]\" and destination register \"lcd:inst\|ADDER_CON\[8\]\" (period= 19.31 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.912 ns + Longest register register " "Info: + Longest register to register delay is 7.912 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|temp2\[9\] 1 REG LC_X11_Y3_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y3_N5; Fanout = 2; REG Node = 'lcd:inst\|temp2\[9\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|temp2[9] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 288 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.914 ns) 1.807 ns lcd:inst\|Equal4~0 2 COMB LC_X11_Y3_N0 1 " "Info: 2: + IC(0.893 ns) + CELL(0.914 ns) = 1.807 ns; Loc. = LC_X11_Y3_N0; Fanout = 1; COMB Node = 'lcd:inst\|Equal4~0'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.807 ns" { lcd:inst|temp2[9] lcd:inst|Equal4~0 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.740 ns) 3.267 ns lcd:inst\|Equal4~2 3 COMB LC_X11_Y3_N3 2 " "Info: 3: + IC(0.720 ns) + CELL(0.740 ns) = 3.267 ns; Loc. = LC_X11_Y3_N3; Fanout = 2; COMB Node = 'lcd:inst\|Equal4~2'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.460 ns" { lcd:inst|Equal4~0 lcd:inst|Equal4~2 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.200 ns) 4.189 ns lcd:inst\|ADDER_CON\[17\]~36 4 COMB LC_X11_Y3_N8 18 " "Info: 4: + IC(0.722 ns) + CELL(0.200 ns) = 4.189 ns; Loc. = LC_X11_Y3_N8; Fanout = 18; COMB Node = 'lcd:inst\|ADDER_CON\[17\]~36'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "0.922 ns" { lcd:inst|Equal4~2 lcd:inst|ADDER_CON[17]~36 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.480 ns) + CELL(1.243 ns) 7.912 ns lcd:inst\|ADDER_CON\[8\] 5 REG LC_X8_Y7_N9 3 " "Info: 5: + IC(2.480 ns) + CELL(1.243 ns) = 7.912 ns; Loc. = LC_X8_Y7_N9; Fanout = 3; REG Node = 'lcd:inst\|ADDER_CON\[8\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.723 ns" { lcd:inst|ADDER_CON[17]~36 lcd:inst|ADDER_CON[8] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.097 ns ( 39.14 % ) " "Info: Total cell delay = 3.097 ns ( 39.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.815 ns ( 60.86 % ) " "Info: Total interconnect delay = 4.815 ns ( 60.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "7.912 ns" { lcd:inst|temp2[9] lcd:inst|Equal4~0 lcd:inst|Equal4~2 lcd:inst|ADDER_CON[17]~36 lcd:inst|ADDER_CON[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "7.912 ns" { lcd:inst|temp2[9] {} lcd:inst|Equal4~0 {} lcd:inst|Equal4~2 {} lcd:inst|ADDER_CON[17]~36 {} lcd:inst|ADDER_CON[8] {} } { 0.000ns 0.893ns 0.720ns 0.722ns 2.480ns } { 0.000ns 0.914ns 0.740ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-10.689 ns - Smallest " "Info: - Smallest clock skew is -10.689 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns lcd:inst\|ADDER_CON\[8\] 2 REG LC_X8_Y7_N9 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y7_N9; Fanout = 3; REG Node = 'lcd:inst\|ADDER_CON\[8\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clkin lcd:inst|ADDER_CON[8] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|ADDER_CON[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|ADDER_CON[8] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 14.370 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 14.370 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns lcd:inst\|CLKOUT 2 REG LC_X9_Y4_N7 16 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X9_Y4_N7; Fanout = 16; REG Node = 'lcd:inst\|CLKOUT'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clkin lcd:inst|CLKOUT } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.682 ns) + CELL(1.294 ns) 9.033 ns lcd:inst\|HSYNC 3 REG LC_X6_Y6_N5 18 " "Info: 3: + IC(3.682 ns) + CELL(1.294 ns) = 9.033 ns; Loc. = LC_X6_Y6_N5; Fanout = 18; REG Node = 'lcd:inst\|HSYNC'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "4.976 ns" { lcd:inst|CLKOUT lcd:inst|HSYNC } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.419 ns) + CELL(0.918 ns) 14.370 ns lcd:inst\|temp2\[9\] 4 REG LC_X11_Y3_N5 2 " "Info: 4: + IC(4.419 ns) + CELL(0.918 ns) = 14.370 ns; Loc. = LC_X11_Y3_N5; Fanout = 2; REG Node = 'lcd:inst\|temp2\[9\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.337 ns" { lcd:inst|HSYNC lcd:inst|temp2[9] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 288 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 32.49 % ) " "Info: Total cell delay = 4.669 ns ( 32.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.701 ns ( 67.51 % ) " "Info: Total interconnect delay = 9.701 ns ( 67.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "14.370 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[9] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "14.370 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[9] {} } { 0.000ns 0.000ns 1.600ns 3.682ns 4.419ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|ADDER_CON[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|ADDER_CON[8] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "14.370 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[9] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "14.370 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[9] {} } { 0.000ns 0.000ns 1.600ns 3.682ns 4.419ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 288 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "7.912 ns" { lcd:inst|temp2[9] lcd:inst|Equal4~0 lcd:inst|Equal4~2 lcd:inst|ADDER_CON[17]~36 lcd:inst|ADDER_CON[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "7.912 ns" { lcd:inst|temp2[9] {} lcd:inst|Equal4~0 {} lcd:inst|Equal4~2 {} lcd:inst|ADDER_CON[17]~36 {} lcd:inst|ADDER_CON[8] {} } { 0.000ns 0.893ns 0.720ns 0.722ns 2.480ns } { 0.000ns 0.914ns 0.740ns 0.200ns 1.243ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|ADDER_CON[8] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|ADDER_CON[8] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "14.370 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[9] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "14.370 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[9] {} } { 0.000ns 0.000ns 1.600ns 3.682ns 4.419ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clkin 25 " "Warning: Circuit may not operate. Detected 25 non-operational path(s) clocked by clock \"clkin\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lcd:inst\|delay lcd:inst\|temp2\[0\] clkin 7.979 ns " "Info: Found hold time violation between source  pin or register \"lcd:inst\|delay\" and destination pin or register \"lcd:inst\|temp2\[0\]\" for clock \"clkin\" (Hold time is 7.979 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "10.689 ns + Largest " "Info: + Largest clock skew is 10.689 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 14.370 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 14.370 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns lcd:inst\|CLKOUT 2 REG LC_X9_Y4_N7 16 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X9_Y4_N7; Fanout = 16; REG Node = 'lcd:inst\|CLKOUT'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clkin lcd:inst|CLKOUT } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.682 ns) + CELL(1.294 ns) 9.033 ns lcd:inst\|HSYNC 3 REG LC_X6_Y6_N5 18 " "Info: 3: + IC(3.682 ns) + CELL(1.294 ns) = 9.033 ns; Loc. = LC_X6_Y6_N5; Fanout = 18; REG Node = 'lcd:inst\|HSYNC'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "4.976 ns" { lcd:inst|CLKOUT lcd:inst|HSYNC } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.419 ns) + CELL(0.918 ns) 14.370 ns lcd:inst\|temp2\[0\] 4 REG LC_X10_Y4_N5 4 " "Info: 4: + IC(4.419 ns) + CELL(0.918 ns) = 14.370 ns; Loc. = LC_X10_Y4_N5; Fanout = 4; REG Node = 'lcd:inst\|temp2\[0\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.337 ns" { lcd:inst|HSYNC lcd:inst|temp2[0] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 288 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 32.49 % ) " "Info: Total cell delay = 4.669 ns ( 32.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.701 ns ( 67.51 % ) " "Info: Total interconnect delay = 9.701 ns ( 67.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "14.370 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "14.370 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[0] {} } { 0.000ns 0.000ns 1.600ns 3.682ns 4.419ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns lcd:inst\|delay 2 REG LC_X9_Y4_N0 46 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X9_Y4_N0; Fanout = 46; REG Node = 'lcd:inst\|delay'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clkin lcd:inst|delay } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|delay } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|delay {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "14.370 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "14.370 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[0] {} } { 0.000ns 0.000ns 1.600ns 3.682ns 4.419ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|delay } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|delay {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.555 ns - Shortest register register " "Info: - Shortest register to register delay is 2.555 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|delay 1 REG LC_X9_Y4_N0 46 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y4_N0; Fanout = 46; REG Node = 'lcd:inst\|delay'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|delay } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.312 ns) + CELL(1.243 ns) 2.555 ns lcd:inst\|temp2\[0\] 2 REG LC_X10_Y4_N5 4 " "Info: 2: + IC(1.312 ns) + CELL(1.243 ns) = 2.555 ns; Loc. = LC_X10_Y4_N5; Fanout = 4; REG Node = 'lcd:inst\|temp2\[0\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.555 ns" { lcd:inst|delay lcd:inst|temp2[0] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 288 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.243 ns ( 48.65 % ) " "Info: Total cell delay = 1.243 ns ( 48.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.312 ns ( 51.35 % ) " "Info: Total interconnect delay = 1.312 ns ( 51.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.555 ns" { lcd:inst|delay lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "2.555 ns" { lcd:inst|delay {} lcd:inst|temp2[0] {} } { 0.000ns 1.312ns } { 0.000ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 288 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "14.370 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "14.370 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|temp2[0] {} } { 0.000ns 0.000ns 1.600ns 3.682ns 4.419ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|delay } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|delay {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.555 ns" { lcd:inst|delay lcd:inst|temp2[0] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "2.555 ns" { lcd:inst|delay {} lcd:inst|temp2[0] {} } { 0.000ns 1.312ns } { 0.000ns 1.243ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "lcd:inst\|DATA\[13\] sram_data\[13\] clkin 2.155 ns register " "Info: tsu for register \"lcd:inst\|DATA\[13\]\" (data pin = \"sram_data\[13\]\", clock pin = \"clkin\") is 2.155 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.503 ns + Longest pin register " "Info: + Longest pin to register delay is 5.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sram_data\[13\] 1 PIN PIN_111 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_111; Fanout = 1; PIN Node = 'sram_data\[13\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { sram_data[13] } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 96 320 498 112 "sram_data\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sram_data~2 2 COMB IOC_X12_Y8_N3 1 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X12_Y8_N3; Fanout = 1; COMB Node = 'sram_data~2'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { sram_data[13] sram_data~2 } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 96 320 498 112 "sram_data\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.310 ns) + CELL(1.061 ns) 5.503 ns lcd:inst\|DATA\[13\] 3 REG LC_X7_Y5_N0 1 " "Info: 3: + IC(3.310 ns) + CELL(1.061 ns) = 5.503 ns; Loc. = LC_X7_Y5_N0; Fanout = 1; REG Node = 'lcd:inst\|DATA\[13\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "4.371 ns" { sram_data~2 lcd:inst|DATA[13] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 39.85 % ) " "Info: Total cell delay = 2.193 ns ( 39.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.310 ns ( 60.15 % ) " "Info: Total interconnect delay = 3.310 ns ( 60.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.503 ns" { sram_data[13] sram_data~2 lcd:inst|DATA[13] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "5.503 ns" { sram_data[13] {} sram_data~2 {} lcd:inst|DATA[13] {} } { 0.000ns 0.000ns 3.310ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns lcd:inst\|DATA\[13\] 2 REG LC_X7_Y5_N0 1 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X7_Y5_N0; Fanout = 1; REG Node = 'lcd:inst\|DATA\[13\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clkin lcd:inst|DATA[13] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|DATA[13] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|DATA[13] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.503 ns" { sram_data[13] sram_data~2 lcd:inst|DATA[13] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "5.503 ns" { sram_data[13] {} sram_data~2 {} lcd:inst|DATA[13] {} } { 0.000ns 0.000ns 3.310ns } { 0.000ns 1.132ns 1.061ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|DATA[13] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|DATA[13] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}