tft.fit.rpt

stm32数码相框

; Router Effort Multiplier                                                   ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                                ; Off                            ; Off                            ;
; Optimize Hold Timing                                                       ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing                                               ; Off                            ; Off                            ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner                     ; On                             ; On                             ;
; PowerPlay Power Optimization                                               ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                            ; Normal compilation             ; Normal compilation             ;
; Optimize Timing for ECOs                                                   ; Off                            ; Off                            ;
; Regenerate full fit report during ECO compiles                             ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                                 ; On                             ; On                             ;
; Limit to One Fitting Attempt                                               ; Off                            ; Off                            ;
; Final Placement Optimizations                                              ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                              ; 1                              ; 1                              ;
; Slow Slew Rate                                                             ; Off                            ; Off                            ;
; PCI I/O                                                                    ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                      ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                                  ; Off                            ; Off                            ;
; Auto Delay Chains                                                          ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                               ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                                  ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                     ; Off                            ; Off                            ;
; Fitter Effort                                                              ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                            ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                           ; Auto                           ;
; Auto Register Duplication                                                  ; Auto                           ; Auto                           ;
; Auto Global Clock                                                          ; On                             ; On                             ;
; Auto Global Register Control Signals                                       ; On                             ; On                             ;
; Stop After Congestion Map Generation                                       ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                          ; Off                            ; Off                            ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                            ; Off                            ;
; Use Best Effort Settings for Compilation                                   ; Off                            ; Off                            ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.25        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;  14.3%      ;
+----------------------------+-------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/570/570_h_speed/TFT.pin.


+------------------------------------------------------------------+
; Fitter Resource Usage Summary                                    ;
+---------------------------------------------+--------------------+
; Resource                                    ; Usage              ;
+---------------------------------------------+--------------------+
; Total logic elements                        ; 357 / 570 ( 63 % ) ;
;     -- Combinational with no register       ; 157                ;
;     -- Register only                        ; 52                 ;
;     -- Combinational with a register        ; 148                ;
;                                             ;                    ;
; Logic element usage by number of LUT inputs ;                    ;
;     -- 4 input functions                    ; 79                 ;
;     -- 3 input functions                    ; 48                 ;
;     -- 2 input functions                    ; 156                ;
;     -- 1 input functions                    ; 22                 ;
;     -- 0 input functions                    ; 0                  ;
;                                             ;                    ;
; Logic elements by mode                      ;                    ;
;     -- normal mode                          ; 242                ;
;     -- arithmetic mode                      ; 115                ;
;     -- qfbk mode                            ; 18                 ;
;     -- register cascade mode                ; 0                  ;
;     -- synchronous clear/load mode          ; 95                 ;
;     -- asynchronous clear/load mode         ; 0                  ;
;                                             ;                    ;
; Total registers                             ; 200 / 570 ( 35 % ) ;
; Total LABs                                  ; 46 / 57 ( 81 % )   ;
; Logic elements in carry chains              ; 123                ;
; User inserted logic elements                ; 0                  ;
; Virtual pins                                ; 0                  ;
; I/O pins                                    ; 72 / 116 ( 62 % )  ;