📄 tft.map.rpt
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; Total registers ; 200 ;
; Total logic cells in carry chains ; 123 ;
; I/O pins ; 72 ;
; Maximum fan-out node ; clkin ;
; Maximum fan-out ; 170 ;
; Total fan-out ; 1338 ;
; Average fan-out ; 2.97 ;
+---------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |TFT ; 379 (0) ; 200 ; 0 ; 72 ; 0 ; 179 (0) ; 74 (0) ; 126 (0) ; 123 (0) ; 0 (0) ; |TFT ; work ;
; |lcd:inst| ; 379 (379) ; 200 ; 0 ; 0 ; 0 ; 179 (179) ; 74 (74) ; 126 (126) ; 123 (123) ; 0 (0) ; |TFT|lcd:inst ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+-----------------------------------------------------------------------+
; State Machine - |TFT|lcd:inst|shi ;
+-----------+-----------+-----------+-----------+-----------+-----------+
; Name ; shi.00011 ; shi.00010 ; shi.00001 ; shi.00000 ; shi.00100 ;
+-----------+-----------+-----------+-----------+-----------+-----------+
; shi.00000 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; shi.00001 ; 0 ; 0 ; 1 ; 1 ; 0 ;
; shi.00010 ; 0 ; 1 ; 0 ; 1 ; 0 ;
; shi.00011 ; 1 ; 0 ; 0 ; 1 ; 0 ;
; shi.00100 ; 0 ; 0 ; 0 ; 1 ; 1 ;
+-----------+-----------+-----------+-----------+-----------+-----------+
Encoding Type: One-Hot
+----------------------------------+
; State Machine - |TFT|lcd:inst|rw ;
+-------+--------------------------+
; Name ; rw.01 ;
+-------+--------------------------+
; rw.00 ; 0 ;
; rw.01 ; 1 ;
+-------+--------------------------+
+---------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+----------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+----------------------------------+
; lcd:inst|rw_data[1..4] ; Merged with lcd:inst|rw_data[0] ;
; lcd:inst|rw_data[6..10] ; Merged with lcd:inst|rw_data[5] ;
; lcd:inst|rw_data[12..15] ; Merged with lcd:inst|rw_data[11] ;
; lcd:inst|read_need ; Merged with lcd:inst|DE ;
; lcd:inst|JGND[0..6] ; Merged with lcd:inst|JGND[7] ;
; lcd:inst|UB ; Merged with lcd:inst|LB ;
; lcd:inst|shi~3 ; Lost fanout ;
; lcd:inst|shi~4 ; Lost fanout ;
; lcd:inst|shi~6 ; Lost fanout ;
; lcd:inst|shi~7 ; Lost fanout ;
; lcd:inst|rw~5 ; Lost fanout ;
; lcd:inst|shi.00000 ; Lost fanout ;
; Total Number of Removed Registers = 28 ; ;
+----------------------------------------+----------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 200 ;
; Number of registers using Synchronous Clear ; 36 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 130 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; lcd:inst|OE ; 2 ;
; lcd:inst|CE ; 3 ;
; lcd:inst|WE ; 3 ;
; lcd:inst|DATA[15] ; 1 ;
; lcd:inst|DATA[14] ; 1 ;
; lcd:inst|DATA[13] ; 1 ;
; lcd:inst|DATA[12] ; 1 ;
; lcd:inst|DATA[11] ; 1 ;
; lcd:inst|DATA[10] ; 1 ;
; lcd:inst|DATA[9] ; 1 ;
; lcd:inst|DATA[8] ; 1 ;
; lcd:inst|DATA[7] ; 1 ;
; lcd:inst|DATA[6] ; 1 ;
; lcd:inst|DATA[5] ; 1 ;
; lcd:inst|DATA[4] ; 1 ;
; lcd:inst|DATA[3] ; 1 ;
; lcd:inst|DATA[2] ; 1 ;
; lcd:inst|DATA[1] ; 1 ;
; lcd:inst|DATA[0] ; 1 ;
; lcd:inst|JGND[7] ; 9 ;
; lcd:inst|in_rw ; 4 ;
; Total number of inverted registers = 21 ; ;
+-----------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; 5:1 ; 10 bits ; 30 LEs ; 10 LEs ; 20 LEs ; Yes ; |TFT|lcd:inst|temp1[2] ;
; 33:1 ; 18 bits ; 396 LEs ; 18 LEs ; 378 LEs ; Yes ; |TFT|lcd:inst|ADDER_CON[4] ;
; 33:1 ; 18 bits ; 396 LEs ; 18 LEs ; 378 LEs ; Yes ; |TFT|lcd:inst|ADDER_TFT[14] ;
; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |TFT|lcd:inst|rw_data[11] ;
; 8:1 ; 5 bits ; 25 LEs ; 15 LEs ; 10 LEs ; No ; |TFT|lcd:inst|shi ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
Info: Processing started: Wed Jan 12 20:45:31 2011
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TFT -c TFT
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file tft.bdf
Info: Found entity 1: TFT
Info: Found 1 design units, including 1 entities, in source file lcd.v
Info: Found entity 1: lcd
Info: Found 1 design units, including 1 entities, in source file lcd_test.v
Info: Found entity 1: lcd_test
Warning (10227): Verilog HDL Port Declaration warning at lcd.v(10): data type declaration for "ADDER" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at lcd.v(5): see declaration for object "ADDER"
Info: Elaborating entity "TFT" for the top level hierarchy
Info: Elaborating entity "lcd" for hierarchy "lcd:inst"
Warning (10036): Verilog HDL or VHDL warning at lcd.v(8): object "TONG" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(14): object "tmp" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(17): object "temp4" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(24): object "rd_data" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at lcd.v(150): truncated value with size 32 to match size of target (18)
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "HL" is stuck at VCC
Info: 6 registers lost all their fanouts during netlist optimizations. The first 6 are displayed below.
Info: Register "lcd:inst|shi~3" lost all its fanouts during netlist optimizations.
Info: Register "lcd:inst|shi~4" lost all its fanouts during netlist optimizations.
Info: Register "lcd:inst|shi~6" lost all its fanouts during netlist optimizations.
Info: Register "lcd:inst|shi~7" lost all its fanouts during netlist optimizations.
Info: Register "lcd:inst|rw~5" lost all its fanouts during netlist optimizations.
Info: Register "lcd:inst|shi.00000" lost all its fanouts during netlist optimizations.
Info: Implemented 451 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 55 output pins
Info: Implemented 16 bidirectional pins
Info: Implemented 379 logic cells
Info: Generated suppressed messages file F:/570/570_h_speed/TFT.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Peak virtual memory: 171 megabytes
Info: Processing ended: Wed Jan 12 20:45:36 2011
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:04
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/570/570_h_speed/TFT.map.smsg.
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