config.h

一个免费的SMART CARD OS系统。

#ifndef TCK_CONFIG__H
/* ============================================================================
   Project Name : jayaCard TCK
   Module Name  : proto/tck/common/config.h
   Version : $Id: config.h,v 1.19 2004/04/23 21:33:44 dgil Exp $

	Description: This is the TCK Configuration File

    The Original Code is jayaCard TCK code.

    The Initial Developer of the Original Code is Gilles Dumortier.

	Portions created by the Initial Developer are Copyright (C) 2002-2004 the
    Initial Developer. All Rights Reserved.

    Contributor(s):

	Permission is granted to any individual to use, copy, or redistribute
	this software so long as all of the original files are included
	unmodified, that it is not sold for profit, and that this copyright
	notice is retained.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

   History Rev	Description
   041003 dgil	wrote it from scratch
   ============================================================================
*/

#define TCK_CONFIG__H

/* =========================================================================
	Crypto
   ========================================================================= */

#define JAYACFG_CIPHER_ALGO_DEFAULT		0x00
#define JAYACFG_HASH_ALGO_DEFAULT		0x00
#define JAYACFG_IV_ZERO
#define JAYACFG_CIPHER_PAD_DEFAULT		0x05	/* emv */

/* =========================================================================
	TCL Default values
   ========================================================================= */

#define JAYACFG_FSCI			0x07	/* 0x07 => 128 bytes */
#define JAYACFG_FWI				0x08	/* Frame Waiting Index => FWT = 80 ms */
#define JAYACFG_MBLI			0x00	/* no information for PCD on frame max size */
#define JAYACFG_BITRATECAP      0x00    /* 1=x2 2=x4 4=x8 */

/* =========================================================================
	AppliData
   ========================================================================= */

#define	JAYACFG_NUM_APPLICATIONS	1

#define JAYACFG_AFI_FAMS_X	0x00
#define JAYACFG_AFI_FAMS_Y	0x00

/* =========================================================================
	Memory base addresses and size
   ========================================================================= */

#define SIZE_OF_XDATA		1024

#define ADDR_OF_BDATA		0x20
#define SIZE_OF_BDATA   	8

#define ADDR_OF_DATAGROUP	0x65
#define SIZE_OF_DATAGROUP   0x30

#define ADDR_OF_XDATAGROUP	0x100
#define SIZE_OF_XDATAGROUP  0x20

#define ADDR_OF_STACK		0x80
#define SIZE_OF_STACK		0x10

#define ADDR_OF_XSTACK      0x140
#define SIZE_OF_XSTACK		0x40

#define BASE_EEPROM			0x4000
#define END_EEPROM			0x7FFF
#define SIZE_EEPROM			(END_EEPROM - BASE_EEPROM + 1)

#define ADDR_CHIP_UUID		0x7FA0

#define BASE_OTP			0x7FB0
#define END_OTP				0x7FBF
#define SIZE_OTP			(END_OTP - BASE_OTP + 1)

#define BASE_MANUFACTURING_DATA	0x7FC0
#define END_MANUFACTURING_DATA	(BASE_MANUFACTURING_DATA+47)
#define SIZE_MANUFACTURING_DATA	(END_MANUFACTURING_DATA - BASE_MANUFACTURING_DATA + 1)

#define ADDR_MSK			(BASE_MANUFACTURING_DATA+16)
#define ADDR_MSK_ATTEMPT	(BASE_MANUFACTURING_DATA+34)

#define ADDR_RANDOM			(BASE_MANUFACTURING_DATA+48)
#define SIZE_RANDOM			(END_MANUFACTURING_DATA - BASE_MANUFACTURING_DATA - 48 + 1)

/* =========================================================================
	Submission Attempts
   ========================================================================= */

#define JAYACFG_SUBMITKEY_MAX		3
#define JAYACFG_SUBMITPASSWORD_MAX	3
#define JAYACFG_SUBMITUNBLOCK_MAX	10

/* ============================================================================
	File System Configuration
   ========================================================================= */

#define ADDR_HEADER_MF			BASE_EEPROM+0x200
#define BASE_HEADER_FILE_ADDR	ADDR_HEADER_MF+SIZE_HEADER_FILE
#define BASE_BODY_FILE_ADDR		END_EEPROM-0x100

#define FREE_HEADER_FILE_ADDR	(BASE_EEPROM+0x0000)
#define FREE_BODY_FILE_ADDR		(BASE_EEPROM+0x0002)

/* ============================================================================
	Stream Configuration
   ========================================================================= */

#define CHUNK_OF_STREAM		8	/* also the size of the input buffer for crypto */

/* ============================================================================
	ATR

	EEPROM_SIZEOF_ATR

	ADDR_EEPROM_ATR
		memory mapping is : L | B1 | ... | BL | ... pad ... | CRClo | CRChi

   ========================================================================= */

#define EEPROM_SIZEOF_ATR	20
#define ADDR_EEPROM_ATR		0x7F04

/* ============================================================================
	ATS

	EEPROM_SIZEOF_ATS

	ADDR_EEPROM_ATS
		memory mapping is : L | B1 | ... | BL | ... pad ... | CRClo | CRChi
   ========================================================================= */

#define EEPROM_SIZEOF_ATS	24
#define ADDR_EEPROM_ATS		0x7F16

/* ============================================================================
	Opcode entry points in EEPROM
   ========================================================================= */

#define ADDR_OPCODE_BASE		0x7F30
#define ADDR_OPCODE_ATR			(ADDR_OPCODE_BASE+0x00)
#define ADDR_OPCODE_ATS			(ADDR_OPCODE_BASE+0x04)
#define ADDR_OPCODE_TCLFSM		(ADDR_OPCODE_BASE+0x08)
#define ADDR_OPCODE_STARTUP		(ADDR_OPCODE_BASE+0x0C)
#define ADDR_OPCODE_DISPATCH	(ADDR_OPCODE_BASE+0x10)
#define ADDR_OPCODE_INIT		(ADDR_OPCODE_BASE+0x18)
#define ADDR_OPCODE_INIT_CIPHER (ADDR_OPCODE_BASE+0x1C)
#define ADDR_OPCODE_HMAC        (ADDR_OPCODE_BASE+0x20)
#define ADDR_OPCODE_SELECT      (ADDR_OPCODE_BASE+0x24)
#define ADDR_OPCODE_DESELECT    (ADDR_OPCODE_BASE+0x28)
#define ADDR_OPCODE_AC_EXT      (ADDR_OPCODE_BASE+0x2C)

/* ============================================================================
	Transaction Area

		SPattern: State | AdrL | AdrH | n | D1 ... Dn | CRCL | CRCH
		TransArea: free pointer | SPattern1 | SPattern2 ... SPatternm | EOT
   ========================================================================= */

#define ADDR_TRANSACTION_FREE		(BASE_EEPROM+0x0006)	/* free pointer */
#define ADDR_TRANSACTION_BEGIN      (BASE_EEPROM+0x0070)
#define ADDR_TRANSACTION_END		(BASE_EEPROM+0x01FF)
#define ADDR_TRANSACTION_AREASIZE	(ADDR_TRANSACTION_END-ADDR_TRANSACTION_BEGIN+1)

#define SIZEOF_TRANSACTION_INFO		(1+2+1+2)

/* ============================================================================
    Configuration Area (12 bytes)
   ========================================================================= */

#define ADDR_BASE_CONFIG       (BASE_EEPROM+0x0008)

/* ============================================================================
    T=CL Buffer Address in XDATA __x XXX move to config
   ========================================================================= */

#define JAYACFG_ADDR_COM_OUT_BUFFER     0x200
#define JAYACFG_ADDR_COM_IN_BUFFER      0x2C5

/* ============================================================================
    Default Chunk for EEPROM write before a WTX is required

    unit is number of CHUNK_OF_STREAM (typ. 8 bytes)
   ========================================================================= */

#define JAYACFG_CHUNK_EEPROM_WRITE_BEFORE_WTX_REQUIRED  32

/* ========================================================================= */

#endif
/* defined TCK_CONFIG__H */