abel3lib.inc

GAL开发工具

    3910

" E0320.INC

	MISER macro (a) { fuses [2912,2913] = [?a,?a]; };

	TURBO macro (a) { fuses [2914,2915] = [?a,?a]; };


" E0600.INC

	TURBO macro (a) { fuses [6480,6481] = [?a,?a]; };


" E0900.INC

	TURBO macro (a) { fuses [17400,17401] = [?a,?a]; };


" E1210.INC
" Clock modes 0,1,2,3 and 4 are supported by the 3.00 SIMULATOR.
"
" The input latches are not modeled in modes 6 and 7.
"
" The output clock polarity is reversed in modes 5 and 7, this
" will not cause any problems if the .C. and .K. are used.
" Clocking with decrete '0's and '1's may produce simulation
" errors.

	CLK_MODE macro (a) { fuses [15144,15143,15142] = ?a;};

	TURBO macro (a) { fuses [15145,15146] = [?a,?a]; };


" E1800.INC

	MISER_CLK_C macro (a) { fuses 42480 = ?a; };
	MISER_CLK_B macro (a) { fuses 42481 = ?a; };
	MISER_CLK_A macro (a) { fuses 42482 = ?a; };
	MISER_CLK_D macro (a) { fuses 42483 = ?a; };
	MISER_IN_C  macro (a) { fuses 42484 = ?a; };
	MISER_IN_B  macro (a) { fuses 42485 = ?a; };
	MISER_IN_A  macro (a) { fuses 42486 = ?a; };
	MISER_IN_D  macro (a) { fuses 42487 = ?a; };

	TURBO macro (a) { fuses [42488,42489] = [?a,?a]; };


" F155.INC

	EA_HIZ macro  { fuses [2106,2107] = [1,1]; };
	EB_HIZ macro  { fuses [2104,2105] = [1,1]; };


" F157.INC

	EA_HIZ macro  { fuses [2106,2107] = [1,1]; };
	EB_HIZ macro  { fuses [2104,2105] = [1,1]; };


" F159.INC

	EA_HIZ macro  { fuses [2104,2105] = [1,1]; };
	EB_HIZ macro  { fuses [2106,2107] = [1,1]; };


" F179.INC

	EA_HIZ macro  { fuses [2450,2451] = [1,1]; };
	EB_HIZ macro  { fuses [2448,2449] = [1,1]; };


" F39V18.INC

	"Input Logic Macro Cell Configuration for F39V18
	" (1,1) Async Input   (default)
	" (1,0) Registered Input
	" (0,0) Latched Input
	ILMC  macro (LATCH,SYN) { FUSES [8219,8218] = [?LATCH,?SYN]; }
	IOLMC macro (LATCH,SYN) { FUSES [8221,8220] = [?LATCH,?SYN]; }


" P16X4.INC
	"These macros are used to create a JEDEC file for the
	"arithmetic PALs such as the 16X4 and 16A4. Valid test
	"vectors can be generated for the device programmer 
	"but ABEL can not simulate these equations.

	"Reduction level -r0 must always be used.

	"Fixed symbol macros
	A          macro (n) { A?n & !A?n};		" (A)
	NA         macro (n) { B?n & !B?n};		" (/A)
	B          macro (n) { B?n &  A?n};		" (B)
	NB         macro (n) {!B?n & !A?n};		" (/B)

	A_OR_B     macro (n) { A?n};			" (A+B)
	NA_OR_B    macro (n) { B?n};			" (/A+B)
	N_OR_NB    macro (n) {!A?n};			" (A+/B)
	NA_OR_NB   macro (n) {!B?n};			" (/A+/B)

	A_AND_B    macro (n) { B?n &  A?n & !A?n};	" (A*B)
	NA_AND_B   macro (n) { B?n & !B?n &  A?n};	" (/A*B)
	A_AND_NB   macro (n) {!B?n &  A?n & !A?n};	" (A*/B)
	NA_AND_NB  macro (n) { B?n & !B?n & !A?n};	" (/A*/B)

	A_XNOR_B   macro (n) { B?n & !A?n}; 		" (A:*:B)
	A_XOR_B    macro (n) {!B?n &  A?n};		" (A:+:B)


" P330.INC
	"The following select Clock 2 (pin 3) for the 
	"Output Macrocell Input register.
	CLK2_28 macro () {FUSES[17030] = 1;}
	CLK2_27 macro () {FUSES[17034] = 1;}
	CLK2_26 macro () {FUSES[17037] = 1;}
	CLK2_25 macro () {FUSES[17041] = 1;}
	CLK2_24 macro () {FUSES[17044] = 1;}
	CLK2_23 macro () {FUSES[17048] = 1;}
	CLK2_20 macro () {FUSES[17051] = 1;}
	CLK2_19 macro () {FUSES[17055] = 1;}
	CLK2_18 macro () {FUSES[17058] = 1;}
	CLK2_17 macro () {FUSES[17062] = 1;}
	CLK2_16 macro () {FUSES[17065] = 1;}
	CLK2_15 macro () {FUSES[17069] = 1;}

	"The following enables clock 2 (pin 3)
	CLK2    macro () {FUSES[17070] = 1;}

	"The following program the C3 bit in the Output Macrocell
	"and selects feedback from the lower pin.
	FEEDPIN_27 macro () {FUSES[17031] = 1;}
	FEEDPIN_25 macro () {FUSES[17038] = 1;}
	FEEDPIN_23 macro () {FUSES[17045] = 1;}
	FEEDPIN_19 macro () {FUSES[17052] = 1;}
	FEEDPIN_17 macro () {FUSES[17059] = 1;}
	FEEDPIN_15 macro () {FUSES[17066] = 1;}

12 
E0320.INC 10 118 ""
E0600.INC 135 66 ""
E0900.INC 206 68 ""
E1210.INC 279 441 ""
E1800.INC 735 437 ""
F155.INC 1186 108 ""
F157.INC 1300 108 ""
F159.INC 1414 108 ""
F179.INC 1528 108 ""
F39V18.INC 1642 276 ""
P16X4.INC 1928 945 ""
P330.INC 2901 980 ""