theatrereg.h

ati driver

			CLKOUT2_SEL_GPIO2_OUT	= 7 << 0,		//   GPIO2_OUT
		CLKOUT2_DRV					= BITS(11:11),	// Set drive strength for CLKOUT2_GPIO2 pin
			CLKOUT2_DRV_8mA			= 0 << 11,		//   8 mA
			CLKOUT2_DRV_4mA			= 1 << 11,		//   4 mA
		CLKOUT1_DIV					= BITS(23:16),	// Postdivider for CLKOUT1
		CLKOUT2_DIV					= BITS(31:24),	// Postdivider for CLKOUT2

	VIP_MASTER_CNTL					= 0x0040,		// Master control
		TV_ASYNC_RST				= BITS(0:0),	//   Reset several blocks that use the TV Clock
		CRT_ASYNC_RST				= BITS(1:1),	//   Reset several blocks that use the CRT Clock
		RESTART_PHASE_FIX			= BITS(3:3),	//
		TV_FIFO_ASYNC_RST			= BITS(4:4),	//
		VIN_ASYNC_RST				= BITS(5:5),	//   Reset several blocks that use the VIN, ADC or SIN Clock
		AUD_ASYNC_RST				= BITS(6:6),	//   Reset several blocks that use the SPDIF or I2S Clock
		DVS_ASYNC_RST				= BITS(7:7),	//   Reset several blocks that use the DVSOUT Clock
		CLKOUT_CLK_SEL				= BITS(8:8),	//   External BYTE clock
		CRT_FIFO_CE_EN				= BITS(9:9),	//
		TV_FIFO_CE_EN				= BITS(10:10),

	VIP_CLKOUT_CNTL					= 0x004c,
		CLKOUT_OE					= BITS(0:0),
		CLKOUT_PUB					= BITS(3:3),
		CLKOUT_PD					= BITS(4:4),
		CLKOUT_DRV					= BITS(5:5),

	VIP_TV_PLL_CNTL					= 0x00c0,
		TV_M0_LO					= BITS(7:0),
		TV_N0_LO					= BITS(16:8),
		TV_M0_HI					= BITS(20:18),
		TV_N0_HI					= BITS(22:21),
		TV_SLIP_EN					= BITS(23:23),
		TV_P						= BITS(27:24),
		TV_DTO_EN					= BITS(28:28),
		TV_DTO_TYPE					= BITS(29:29),
		TV_REF_CLK_SEL				= BITS(31:30),

	VIP_CRT_PLL_CNTL				= 0x00c4,
		CRT_M0_LO					= BITS(7:0),
		CRT_N0_LO					= BITS(16:8),
		CRT_M0_HI					= BITS(20:18),
		CRT_N0_HI					= BITS(22:21),
		CRTCLK_USE_CLKBY2			= BITS(25:25),
		CRT_MNFLIP_EN				= BITS(26:26),
		CRT_SLIP_EN					= BITS(27:27),
		CRT_DTO_EN					= BITS(28:28),
		CRT_DTO_TYPE				= BITS(29:29),
		CRT_REF_CLK_SEL				= BITS(31:30),

	VIP_PLL_CNTL0					= 0x00c8,
		TVRST						= BITS(1:1),
		CRTRST						= BITS(2:2),
		TVSLEEPB					= BITS(3:3),
		CRTSLEEPB					= BITS(4:4),
		TVPCP						= BITS(10:8),
		TVPVG						= BITS(12:11),
		TVPDC						= BITS(15:13),
		CRTPCP						= BITS(18:16),
		CRTPVG						= BITS(20:19),
		CRTPDC						= BITS(23:21),
		CKMONEN						= BITS(24:24),

	VIP_PLL_TEST_CNTL				= 0x00cc,
		PLL_TEST					= BITS(0:0),
		PLL_TST_RST					= BITS(1:1),
		PLL_TST_DIV					= BITS(2:2),
		PLL_TST_CNT_RST				= BITS(3:3),
		STOP_REF_CLK				= BITS(7:7),
		PLL_TST_SEL					= BITS(13:8),
		PLL_TEST_COUNT				= BITS(31:16),

	VIP_CLOCK_SEL_CNTL				= 0x00d0,
		TV_CLK_SEL					= BITS(0:0),
		CRT_CLK_SEL					= BITS(1:1),
		BYT_CLK_SEL					= BITS(3:2),
		PIX_CLK_SEL					= BITS(4:4),
		REG_CLK_SEL					= BITS(5:5),
		TST_CLK_SEL					= BITS(6:6),
		VIN_CLK_SEL					= BITS(7:7),	// Select VIN clock
			VIN_CLK_SEL_REF_CLK		= 0 << 7,		//   Select reference clock
			VIN_CLK_SEL_VIPLL_CLK	= 1 << 7,		//   Select VIN PLL clock
		BYT_CLK_DEL					= BITS(10:8),
		AUD_CLK_SEL					= BITS(11:11),
		L54_CLK_SEL					= BITS(12:12),
		MV_ZONE_1_PHASE				= BITS(13:13),
		MV_ZONE_2_PHASE				= BITS(14:14),
		MV_ZONE_3_PHASE				= BITS(15:15),

	VIP_VIN_PLL_CNTL				= 0x00d4,		// VIN PLL control
		VIN_M0						= BITS(10:0),	//   Reference divider
		VIN_N0						= BITS(21:11),	//   Feedback divider
		VIN_MNFLIP_EN				= BITS(22:22),	//   M/N flip enable
		VIN_P						= BITS(27:24),	//   Post divider
		VIN_REF_CLK_SEL				= BITS(31:30),	//   VIN reference source select
			VIN_REF_CLK				= 0 << 30,		//     Reference clock
			VIN_SEC_REF_CLK			= 1 << 30,		//     Secondary Reference Clock
			VIN_L54_CLK				= 2 << 30,		//     L54 PLL Clock
			VIN_SLIP_L54_CLK		= 3 << 30,		//     Slippable L54 PLL Clock

	VIP_VIN_PLL_FINE_CNTL			= 0x00d8,
		VIN_M1						= BITS(10:0),
		VIN_N1						= BITS(21:11),
		VIN_DIVIDER_SEL				= BITS(22:22),
		VIN_MNFLIP_REQ				= BITS(23:23),
		VIN_MNFLIP_DONE				= BITS(24:24),
		TV_LOCK_TO_VIN				= BITS(27:27),
		TV_P_FOR_VINCLK				= BITS(31:28),

	VIP_AUD_PLL_CNTL				= 0x00e0,
		AUD_M0						= BITS(10:0),
		AUD_N0						= BITS(21:11),
		AUD_MNFLIP_EN				= BITS(22:22),
		AUD_SLIP_EN					= BITS(23:23),
		AUD_P						= BITS(27:24),
		AUD_DTO_EN					= BITS(28:28),
		AUD_DTO_TYPE				= BITS(29:29),
		AUD_REF_CLK_SEL				= BITS(31:30),

	VIP_AUD_PLL_FINE_CNTL			= 0x00e4,
		AUD_M1						= BITS(10:0),
		AUD_N1						= BITS(21:11),
		AUD_DIVIDER_SEL				= BITS(22:22),
		AUD_MNFLIP_REQ				= BITS(23:23),
		AUD_MNFLIP_DONE				= BITS(24:24),
		AUD_SLIP_REQ				= BITS(25:25),
		AID_SLIP_DONE				= BITS(26:26),
		AUD_SLIP_COUNT				= BITS(31:28),

	VIP_AUD_CLK_DIVIDERS			= 0x00e8,
		SPDIF_P						= BITS(3:0),
		I2S_P						= BITS(7:4),
		DIV_AUD_P					= BITS(11:8),

	VIP_AUD_DTO_INCREMENTS			= 0x00ec,
		AUD_DTO_INC0				= BITS(15:0),
		AUD_DTO_INC1				= BITS(31:16),

	VIP_L54_PLL_CNTL				= 0x00f0,
		L54_M0						= BITS(7:0),
		L54_N0						= BITS(21:11),
		L54_MNFLIP_EN				= BITS(22:22),
		L54_SLIP_EN					= BITS(23:23),
		L54_P						= BITS(27:24),
		L54_DTO_EN					= BITS(28:28),
		L54_DTO_TYPE				= BITS(29:29),
		L54_REF_CLK_SEL				= BITS(30:30),

	VIP_L54_PLL_FINE_CNTL			= 0x00f4,
		L54_M1						= BITS(7:0),
		L54_N1						= BITS(21:11),
		L54_DIVIDER_SEL				= BITS(22:22),
		L54_MNFLIP_REQ				= BITS(23:23),
		L54_MNFLIP_DONE				= BITS(24:24),
		L54_SLIP_REQ				= BITS(25:25),
		L54_SLIP_DONE				= BITS(26:26),
		L54_SLIP_COUNT				= BITS(31:28),

	VIP_L54_DTO_INCREMENTS			= 0x00f8,
		L54_DTO_INC0				= BITS(15:0),
		L54_DTO_INC1				= BITS(31:16),

	VIP_PLL_CNTL1					= 0x00fc,
		VINRST						= BITS(1:1),	// 0=active, 1=reset
		AUDRST						= BITS(2:2),
		L54RST						= BITS(3:3),
		VINSLEEPB					= BITS(4:4),
		AUDSLEEPB					= BITS(5:5),
		L54SLEEPB					= BITS(6:6),
		VINPCP						= BITS(10:8),
		VINPVG						= BITS(12:11),
		VINPDC						= BITS(15:13),
		AUDPCP						= BITS(18:16),
		AUDPVG						= BITS(20:19),
		L54PCP						= BITS(26:24),
		L54PVG						= BITS(28:27),
		L54PDC						= BITS(31:29),

	// Audio Interfaces
	VIP_FIFOA_CONFIG				= 0x0800,
		ENT_FIFOA					= BITS(8:0),
		START_FIFOA					= BITS(17:16),
			START_FIFOA_ADDR_0		= 0 << 16,
			START_FIFOA_ADDR_64		= 1 << 16,
			START_FIFOA_ADDR_128	= 2 << 16,
			START_FIFOA_ADDR_192	= 3 << 16,
		END_FIFOA					= BITS(19:18),
			END_FIFOA_ADDR_63		= 0 << 18,
			END_FIFOA_ADDR_127		= 1 << 18,
			END_FIFOA_ADDR_191		= 2 << 18,
			END_FIFOA_ADDR_255		= 3 << 18,
		TEST_EN_FIFOA				= BITS(20:20),
		RST_FIFOA					= BITS(21:21),
		WT_FIFOA_FULL				= BITS(22:22),
		EMPTY_FIFOA					= BITS(23:23),

	VIP_FIFOB_CONFIG				= 0x0804,
		ENT_FIFOB					= BITS(8:0),
		START_FIFOB					= BITS(17:16),
		END_FIFOB					= BITS(19:18),
		TEST_EN_FIFOB				= BITS(20:20),
		RST_FIFOB					= BITS(21:21),
		WT_FIFOB_FULL				= BITS(22:22),
		EMPTY_FIFOB					= BITS(23:23),

	VIP_FIFOC_CONFIG				= 0x0808,
		ENT_FIFOC					= BITS(8:0),
		START_FIFOC					= BITS(17:16),
		END_FIFOC					= BITS(19:18),
		TEST_EN_FIFOC				= BITS(20:20),
		RST_FIFOC					= BITS(21:21),
		WT_FIFOC_FULL				= BITS(22:22),
		EMPTY_FIFOC					= BITS(23:23),

	VIP_SPDIF_PORT_CNTL				= 0x080c,
		SPDIF_PORT_EN				= BITS(0:0),
		AC3_BURST_TRIGGER			= BITS(1:1),
		AC3_BURST_ACTIVE			= BITS(2:2),
		AC3_STREAM_MODE				= BITS(3:3),
		SWAP_AC3_ORDER				= BITS(4:4),
		TX_ON_NOT_EMPTY				= BITS(5:5),
		SPDIF_UNDERFLOW_CLEAR		= BITS(6:6),
		SPDIF_UNDERFLOW				= BITS(7:7),
		SPDIF_UNDERFLOW_CNT			= BITS(15:8),
		SPDIF_OE					= BITS(16:16),
		SPDIF_DRV					= BITS(19:19),
		PREAMBLE_AND_IDLE_SW		= BITS(24:24),

	VIP_SPDIF_CHANNEL_STAT			= 0x0810,
		SPDIF_STATUS_BLOCK			= BITS(0:0),
		SPDIF_DATA_TYPE				= BITS(1:1),
		SPDIF_DIGITAL_COPY			= BITS(2:2),
		SPDIF_PREEMPHASIS			= BITS(5:3),
		SPDIF_MODE					= BITS(7:6),
		SPDIF_CATEGORY				= BITS(15:8),
		SPDIF_SRC_NUM				= BITS(19:16),
		SPDIF_NUM_CHANNELS			= BITS(23:20),
		SPDIF_SAMP_FREQ				= BITS(27:24),
		SPDIF_CLOCK_ACC				= BITS(29:28),

	VIP_SPDIF_AC3_PREAMBLE			= 0x0814,
		AC3_DATA_TYPE				= BITS(4:0),
		AC3_ERR_FLAG				= BITS(7:7),
		AC3_DATA_DEPEN				= BITS(12:8),
		AC3_STREAM_NUM				= BITS(15:13),
		AC3_LENGTH_CODE				= BITS(31:16),

	VIP_I2S_TRANSMIT_CNTL			= 0x0818,
		IISTX_PORT_EN				= BITS(0:0),
		IISTX_UNDERFLOW_CLEAR		= BITS(6:6),
		IISTX_UNDERFLOW				= BITS(7:7),
		IISTX_UNDERFLOW_FRAMES		= BITS(15:8),
		IIS_BITS_PER_CHAN			= BITS(21:16),
		IIS_SLAVE_EN				= BITS(24:24),
		IIS_LOOPBACK_EN				= BITS(25:25),
		ADO_OE						= BITS(26:26),
		ADIO_OE						= BITS(29:29),
		WS_OE						= BITS(30:30),
		BITCLK_OE					= BITS(31:31),

	VIP_I2S_RECEIVE_CNTL			= 0x081c,
		IISRX_PORT_EN				= BITS(0:0),
		LOOPBACK_NO_UNDERFLOW		= BITS(5:5),
		IISRX_OVERFLOW_CLEAR		= BITS(6:6),
		IISRX_OVERFLOW				= BITS(7:7),
		IISRX_OVERFLOW_FRAMES		= BITS(15:8),

	VIP_SPDIF_TX_CNT_REG			= 0x0820,
		SPDIF_TX_CNT				= BITS(23:0),
		SPDIF_TX_CNT_CLR			= BITS(24:24),

	VIP_IIS_TX_CNT_REG				= 0x0824,
		IIS_TX_CNT					= BITS(23:0),
		IIS_TX_CNT_CLR				= BITS(24:24),

	// Miscellaneous Registers
	VIP_HW_DEBUG					= 0x0010,
		HW_DEBUG_TBD				= BITS(15:0),

	VIP_SW_SCRATCH					= 0x0014,
		SW_SCRATCH_TBD				= BITS(15:0),

	VIP_I2C_CNTL_0					= 0x0020,
		I2C_DONE					= BITS(0:0),
		I2C_NACK					= BITS(1:1),
		I2C_HALT					= BITS(2:2),
		I2C_SOFT_RST				= BITS(5:5),
		SDA_DRIVE_EN				= BITS(6:6),
		I2C_DRIVE_SEL				= BITS(7:7),
		I2C_START					= BITS(8:8),
		I2C_STOP					= BITS(9:9),
		I2C_RECEIVE					= BITS(10:10),
		I2C_ABORT					= BITS(11:11),
		I2C_GO						= BITS(12:12),
		I2C_PRESCALE				= BITS(31:16),

	VIP_I2C_CNTL_1					= 0x0024,
		I2C_DATA_COUNT				= BITS(3:0),
		I2C_ADDR_COUNT				= BITS(10:8),
		SCL_DRIVE_EN				= BITS(16:16),
		I2C_SEL						= BITS(17:17),
		I2C_TIME_LIMIT				= BITS(31:24),

	VIP_I2C_DATA					= 0x0028,
		I2C_DATA					= BITS(7:0),

	VIP_INT_CNTL					= 0x002c,
		I2C_INT_EN					= BITS(0:0),
		SPDIF_UF_INT_EN				= BITS(1:1),
		IISTX_UF_INT_EN				= BITS(2:2),
		IISTX_OF_INT_EN				= BITS(3:3),
		VIN_VSYNC_INT_EN			= BITS(4:4),
		VIN_VACTIVE_END_INT_EN		= BITS(5:5),
		VSYNC_DIFF_OVER_LIMIT_INT_EN= BITS(6:6),
		I2C_INT_AK					= BITS(16:16),
		I2C_INT						= BITS(16:16),
		SPDIF_UF_INT_AK				= BITS(17:17),
		SPDIF_UF_INT				= BITS(17:17),
		IISTX_UF_INT_AK				= BITS(18:18),
		IISTX_UF_INT				= BITS(18:18),
		IISRX_OF_INT_AK				= BITS(19:19),
		IISRX_OF_INT				= BITS(19:19),
		VIN_VSYNC_INT_AK			= BITS(20:20),
		VIN_VSYNC_INT				= BITS(20:20),
		VIN_VACTIVE_END_INT_AK		= BITS(21:21),
		VIN_VACTIVE_END_INT			= BITS(21:21),
		VSYNC_DIFF_OVER_LIMIT_INT_AK= BITS(22:22),
		VSYNC_DIFF_OVER_LIMIT_INT	= BITS(22:22),

	VIP_GPIO_INOUT					= 0x0030,
		CLKOUT0_GPIO0_OUT			= BITS(0:0),
		CLKOUT0_GPIO1_OUT			= BITS(1:1),
		CLKOUT0_GPIO2_OUT			= BITS(2:2),
		GPIO_6TO3_OUT				= BITS(6:3),
		SPDIF_GPIO_OUT				= BITS(7:7),
		ADO_GPIO_OUT				= BITS(8:8),
		ADIO_GPIO_OUT				= BITS(9:9),
		WS_GPIO_OUT					= BITS(10:10),
		BITCLK_GPIO_OUT				= BITS(11:11),
		HAD_GPIO_OUT				= BITS(13:12),
		CLKOUT0_GPIO0_IN			= BITS(16:16),
		CLKOUT0_GPIO1_IN			= BITS(17:17),
		CLKOUT0_GPIO2_IN			= BITS(18:18),
		GPIO_6TO3_IN				= BITS(22:19),
		SPDIF_GPIO_IN				= BITS(23:23),
		ADO_GPIO_IN					= BITS(24:24),
		ADIO_GPIO_IN				= BITS(25:25),
		WS_GPIO_IN					= BITS(26:26),
		BITCLK_GPIO_IN				= BITS(27:27),
		HAD_GPIO_IN					= BITS(29:28),

	VIP_GPIO_CNTL					= 0x0034,
		CLKOUT0_GPIO0_OE			= BITS(0:0),
		CLKOUT1_GPIO1_OE			= BITS(1:1),
		CLKOUT2_GPIO2_OE			= BITS(2:2),
		GPIO_6TO3_OE				= BITS(6:3),
		SPDIF_GPIO_OE				= BITS(7:7),
		ADO_GPIO_OE					= BITS(8:8),
		ADIO_GPIO_OE				= BITS(9:9),
		WS_GPIO_OE					= BITS(10:10),
		BITCLK_GPIO_OE				= BITS(11:11),
		HAD_GPIO_OE					= BITS(13:12),
		GPIO_6TO1_STRAPS			= BITS(22:17),

	VIP_RIPINTF_PORT_CNTL			= 0x003c,
		MPP_DATA_DRV				= BITS(2:2),
		HAD_DRV						= BITS(3:3),
		HCTL_DRV					= BITS(4:4),
		SRDY_IRQb_DRV				= BITS(5:5),
		SUB_SYS_ID_EN				= BITS(16:16),

	VIP_DECODER_DEBUG_CNTL			= 0x05d4,
		CHIP_DEBUG_SEL				= BITS(7:0),
		CHIP_DEBUG_EN				= BITS(8:8),
		DECODER_DEBUG_SEL			= BITS(15:12),

	VIP_SINGLE_STEP_DATA			= 0x05d8,
		SS_C						= BITS(7:0),
		SS_Y						= BITS(15:8),

	VIP_I2C_CNTL					= 0x0054,
		I2C_CLK_OE					= BITS(0:0),
		I2C_CLK_OUT					= BITS(1:1),
		I2C_CLK_IN					= BITS(2:2),
		I2C_DAT_OE					= BITS(4:4),
		I2C_DAT_OUT					= BITS(5:5),
		I2C_DAT_IN					= BITS(6:6),
		I2C_CLK_PUB					= BITS(8:8),
		I2C_CLK_PD					= BITS(9:9),
		I2C_CLK_DRV					= BITS(10:10),
		I2C_DAT_PUB					= BITS(12:12),
		I2C_DAT_PD					= BITS(13:13),
		I2C_DAT_DRV					= BITS(14:14),
		I2C_CLK_MX					= BITS(19:16),
		I2C_DAT_MX					= BITS(23:20),
		DELAY_TEST_MODE				= BITS(25:24),

	// Undocumented Registers
	VIP_TV_PLL_FINE_CNTL			= 0x00b8,
	VIP_CRT_PLL_FINE_CNTL			= 0x00bc,
	VIP_MV_MODE_CNTL				= 0x0208,
	VIP_MV_STRIPE_CNTL				= 0x020c,
	VIP_MV_LEVEL_CNTL1				= 0x0210,
	VIP_MV_LEVEL_CNTL2				= 0x0214,
	VIP_MV_STATUS					= 0x0330,
	VIP_TV_DTO_INCREMENTS			= 0x0390,
	VIP_CRT_DTO_INCREMENTS			= 0x0394,
	VIP_VSYNC_DIFF_CNTL				= 0x03a0,
	VIP_VSYNC_DIFF_LIMITS			= 0x03a4,
	VIP_VSYNC_DIFF_RD_DATA			= 0x03a8
};

#endif