theatrereg.h

ati driver

		COMB_COUTSEL				= BITS(22:21),
		COMB_SUMDIFF0SEL			= BITS(23:23),
		COMB_SUMDIFF1SEL			= BITS(25:24),
		COMB_YVLPFSEL				= BITS(26:26),
		COMB_DLYLINESEL				= BITS(28:27),
		COMB_YDLYINSEL				= BITS(30:29),
		COMB_YSUBBW					= BITS(31:31),

	VIP_COMB_CNTL1					= 0x0444,
		COMB_YDLYOUTSEL				= BITS(1:0),
		COMB_CORESIZE				= BITS(3:2),
		COMB_YSUBEN					= BITS(4:4),
		COMB_YOUTSEL				= BITS(5:5),
		COMB_SYNCLPFSEL				= BITS(7:6),
		COMB_SYNCLPFRST				= BITS(8:8),
		COMB_DEBUG					= BITS(9:9),

	VIP_COMB_CNTL2					= 0x0448,
		COMB_HYK0					= BITS(7:0),
		COMB_VYK0					= BITS(15:8),
		COMB_HYK1					= BITS(23:16),
		COMB_VYK1					= BITS(31:24),

	VIP_COMB_LINE_LENGTH			= 0x044c,
		COMB_TAP0LENGTH				= BITS(10:0),
		COMB_TAP1LENGTH				= BITS(27:16),

	VIP_NOISE_CNTL0					= 0x0450,
		NR_EN						= BITS(0:0),
		NR_GAIN_CNTL				= BITS(3:1),
		NR_BW_TRESH					= BITS(9:4),
		NR_GC_TRESH					= BITS(14:10),
		NR_COEF_DESPEC_IMODE		= BITS(15:15),

	// Video Decoder ADC Control
	VIP_ADC_CNTL					= 0x0400,
		INPUT_SELECT				= BITS(2:0),	// Video input mux select
			INPUT_SELECT_COMP0		= 0 << 0,		//   Tuner
			INPUT_SELECT_COMP1		= 1 << 0,		//   Front Comp1
			INPUT_SELECT_COMP2		= 2 << 0,		//   Rear Comp1
			INPUT_SELECT_YF_COMP3	= 3 << 0,		//   Front Comp2
			INPUT_SELECT_YR_COMP4	= 4 << 0,		//   Rear Comp2
			INPUT_SELECT_YCF_COMP3	= 5 << 0,		//   Front YC
			INPUT_SELECT_YCR_COMP4	= 6 << 0,		//   Rear YC
		I_CLAMP_SEL					= BITS(4:3),	// Clamp charge-pump current select
			I_CLAMP_SEL_0_3			= 0 << 3,		//   0.3 uA
			I_CLAMP_SEL_7			= 1 << 3,		//   7.0 uA
			I_CLAMP_SEL_15			= 2 << 3,		//   15.0 uA
			I_CLAMP_SEL_22			= 3 << 3,		//   22.0 uA
		I_AGC_SEL					= BITS(6:5),	// AGC charge-pump current select
			I_AGC_SEL_0_3			= 0 << 5,		//   0.3 uA
			I_AGC_SEL_7				= 1 << 5,		//   7.0 uA
			I_AGC_SEL_15			= 2 << 5,		//   15.0 uA
			I_AGC_SEL_22			= 3 << 5,		//   22.0 uA
		ADC_PDWN					= BITS(7:7),	// AGC power-down select
			ADC_PDWN_UP				= 0 << 7,		//   Power up (for capture mode)
			ADC_PDWN_DOWN			= 1 << 7,		//   Power down
		EXT_CLAMP_CAP				= BITS(8:8),	// Clamp charge cap select
			EXT_CLAMP_CAP_INTERNAL	= 0 << 8,		//   Use internal Clamp Cap.
			EXT_CLAMP_CAP_EXTERNAL	= 1 << 8,		//   Use external Clamp Cap.
		EXT_AGC_CAP					= BITS(9:9),	// AGC charge Cap. select
			EXT_AGC_CAP_INTERNAL	= 0 << 9,		//   Use internal AGC Cap.
			EXT_AGC_CAP_EXTERNAL	= 1 << 9,		//   Use external AGC Cap.
		ADC_DECI_BYPASS				= BITS(10:10),	// ADC video data decimation filter select
			ADC_DECI_WITH_FILTER	= 0 << 10,		//   Decimate ADC data with filtering
			ADC_DECI_WITHOUT_FILTER	= 1 << 10,		//   Decimate ADC data with no filtering
		VBI_DECI_BYPASS				= BITS(11:11),	// ADC VBI data decimation filter select
			VBI_DECI_WITH_FILTER	= 0 << 11,		//   Decimate VBI data from ADC with filtering
			VBI_DECI_WITHOUT_FILTER	= 1 << 11,		//   Decimate VBI data from ADC with no filtering
		DECI_DITHER_EN				= BITS(12:12),	// Decimation filter output dither enable
		ADC_CLK_SEL					= BITS(13:13),	// ADC clock select
			ADC_CLK_SEL_4X			= 0 << 13,		//   Run ADC at 4x Fsc
			ADC_CLK_SEL_8X			= 1 << 13,		//   Run ADC at 8x Fsc
		ADC_BYPASS					= BITS(15:14),	// ADC data path select
			ADC_BYPASS_INTERNAL		= 0 << 14,		//   Use internal ADC
			ADC_BYPASS_EXTERNAL		= 1 << 14,		//   Use external ADC
			ADC_BYPASS_SINGLE		= 2 << 14,		//   Use single step data
		ADC_CH_GAIN_SEL				= BITS(17:16),	// Analog Chroma gain select
			ADC_CH_GAIN_SEL_NTSC	= 0 << 16,		//   Set chroma gain for NTSC
			ADC_CH_GAIN_SEL_PAL		= 1 << 16,		//   Set chroma gain for PAL
		ADC_PAICM					= BITS(19:18),	// AMP common mode voltage select
		ADC_PDCBIAS					= BITS(21:20),	// DC 1.5V bias programmable select
		ADC_PREFHI					= BITS(23:22),	// ADC voltage reference high
			ADC_PREFHI_2_7			= 0 << 22,		//   2.7V (recommended)
			ADC_PREFHI_2_6			= 1 << 22,		//   2.6V
			ADC_PREFHI_2_5			= 2 << 22,		//   2.5V
			ADC_PREFHI_2_4			= 3 << 22,		//   2.4V
		ADC_PREFLO					= BITS(25:24),	// ADC voltage reference low
			ADC_PREFLO_1_8			= 0 << 24,		//   1.8V
			ADC_PREFLO_1_7			= 1 << 24,		//   1.7V
			ADC_PREFLO_1_6			= 2 << 24,		//   1.6V
			ADC_PREFLO_1_5			= 3 << 24,		//   1.5V (recommended)
		ADC_IMUXOFF					= BITS(26:26),
		ADC_CPRESET					= BITS(27:27),	// AGC charge pump reset

	VIP_ADC_DEBUG					= 0x0404,
		ADC_PTST					= BITS(0:0),	// AGC test mode enable
		ADC_PYPDN					= BITS(1:1),
		ADC_PCPDN					= BITS(2:2),	// Chroma AGC path power down mode
		ADC_PTSTA0					= BITS(3:3),	// AGC test mux A select bit 0
		ADC_PTSTA1					= BITS(4:4),	// AGC test mux A select bit 1
		ADC_PTSTB0					= BITS(5:5),	// AGC test mux B select bit 0
		ADC_PTSTB1					= BITS(6:6),	// AGC test mux B select bit 1
		ADC_TSTADC					= BITS(7:7),	// Luma & Chroma ADC test mode
		ADC_TSTPROBEY				= BITS(8:8),	// Luma AGC/ADC test mode
		ADC_TSTPROBEC				= BITS(9:9),	// Chroma AGC/ADC test mode
		ADC_TSTPROBEADC				= BITS(10:10),	// Chroma ADC test structure probe mode
		ADC_TSTADCBIAS				= BITS(11:11),	// Chroma ADC bias node probe mode
		ADC_TSTADCREFM				= BITS(12:12),	// Middle reference point for Luma & Chroma ADC probe
		ADC_TSTADCFBP				= BITS(13:13),	// Chroma ADC folding block positive output probe mode
		ADC_TSTADCFBN				= BITS(14:14),	// Chroma ADC folding block negative output probe mode
		ADC_TSTADCCMP1				= BITS(15:15),	// Chroma ADC comparator #1 output probe mode
		ADC_TSTADCCMP9				= BITS(16:16),	// Chroma ADC comparator #9 output probe mode
		ADC_TSTADCCMP17				= BITS(17:17),	// Chroma ADC comparator #19 output probe mode
		ADC_TSTADCLATCH				= BITS(18:18),	// Dummy latch test mode
		ADC_TSTADCCOMP				= BITS(19:19),	// Dummy comparator test mode

	VIP_THERMO2BIN_STATUS			= 0x040c,
		YOVERFLOW					= BITS(0:0),
		YUNDERFLOW					= BITS(1:1),
		YMSB_LOW_BY_ONE				= BITS(2:2),
		YMSB_HI_BY_ONE				= BITS(3:3),
		COVERFLOW					= BITS(4:4),
		CUNDERFLOW					= BITS(5:5),
		CMSB_LOW_BY_ONE				= BITS(6:6),
		CMSB_HI_BY_ONE				= BITS(7:7),

	// Video Decoder Sync Generator
	VIP_SG_BLACK_GATE				= 0x04c0,		// horizontal blank
		BLANK_INT_START				= BITS(7:0),	//   start of horizontal blank (49)
		BLANK_INT_LENGTH			= BITS(11:8),

	VIP_SG_SYNCTIP_GATE				= 0x04c4,		// synctip pulse
		SYNC_TIP_START				= BITS(10:0),	//   start of sync pulse (882)
		SYNC_TIP_LENGTH				= BITS(15:12),

	VIP_SG_UVGATE_GATE				= 0x04c8,		// chroma burst
		UV_INT_START				= BITS(7:0),	//   start of chroma burst (59)
		U_INT_LENGTH				= BITS(11:8),
		V_INT_LENGTH				= BITS(15:12),

	// Video Decoder Luminance Processor
	VIP_LP_AGC_CLAMP_CNTL0			= 0x0500,		// Luma AGC Clamp control
		SYNCTIP_REF0				= BITS(7:0),	//   40 IRE reference
		SYNCTIP_REF1				= BITS(15:8),
		CLAMP_REF					= BITS(23:16),
		AGC_PEAKWHITE				= BITS(31:24),

	VIP_LP_AGC_CLAMP_CNTL1			= 0x0504,		// Luma AGC Clamp control
		VBI_PEAKWHITE				= BITS(7:0),	//
		CLAMPLOOP_EN				= BITS(24:24),	//   Run Clamp loop
		CLAMPLOOP_INV				= BITS(25:25),	//   Negative Clamp Loop
		AGCLOOP_EN					= BITS(26:26),	//   Run AGC loop
		AGCLOOP_INV					= BITS(27:27),	//   Negative AGC loop

	VIP_LP_BRIGHTNESS				= 0x0508,		// Luma Brightness control
		BRIGHTNESS					= BITS(13:0),	//   Brightness level
		LUMAFLT_SEL					= BITS(15:15),	//   Select flat filter

	VIP_LP_CONTRAST					= 0x050c,		// Luma Contrast level
		CONTRAST					= BITS(7:0),	//   Contrast level
		DITHER_SEL					= BITS(9:8),	//   Dither selection
			DITHER_SEL_TRUNC		= 0 << 8,		//     Truncation
			DITHER_SEL_ROUND		= 1 << 8,		//     Round
			DITHER_SEL_4BIT			= 2 << 8,		//     4 bit error
			DITHER_SEL_9BIT			= 3 << 9,		//     9 bit error

	VIP_LP_SLICE_LIMIT				= 0x0510,
		SLICE_LIMIT_HI				= BITS(7:0),
		SLICE_LIMIT_LO				= BITS(15:8),
		SLICE_LIMIT					= BITS(23:16),

	VIP_LP_WPA_CNTL0				= 0x0514,
		WPA_THRESHOLD				= BITS(10:0),

	VIP_LP_WPA_CNTL1				= 0x0518,
		WPA_TRIGGER_LO				= BITS(9:0),
		WPA_TRIGGER_HI				= BITS(25:16),

	VIP_LP_BLACK_LEVEL				= 0x051c,
		BLACK_LEVEL					= BITS(12:0),

	VIP_LP_SLICE_LEVEL				= 0x0520,
		SLICE_LEVEL					= BITS(7:0),

	VIP_LP_SYNCTIP_LEVEL			= 0x0524,
		SYNCTIP_LEVEL				= BITS(12:0),

	VIP_LP_VERT_LOCKOUT				= 0x0528,
		LP_LOCKOUT_START			= BITS(9:0),
		LP_LOCKOUT_END				= BITS(25:16),

	// Video Decoder Vertical Sync Detector/Counter
	VIP_VS_DETECTOR_CNTL			= 0x0540,
		VSYNC_INT_TRIGGER			= BITS(10:0),
		VSYNC_INT_HOLD				= BITS(26:16),

	VIP_VS_BLANKING_CNTL			= 0x0544,
		VS_FIELD_BLANK_START		= BITS(9:0),
		VS_FIELD_BLANK_END			= BITS(25:16),

	VIP_VS_FIELD_ID_CNTL			= 0x0548,
		VS_FIELD_ID_LOCATION		= BITS(8:0),

	VIP_VS_COUNTER_CNTL				= 0x054c,		// Vertical Sync Counter control
		FIELD_DETECT_MODE			= BITS(1:0),	//   Field detection mode
			FIELD_DETECT_ARTIFICIAL	= 0 << 0,		//     Use artificial field
			FIELD_DETECT_DETECTED	= 1 << 0,		//     Use detected field
			FIELD_DETECT_AUTO		= 2 << 0,		//     Auto switch to Artificial if interlace is lost
			FIELD_DETECT_FORCE		= 3 << 0,		//     Use field force bit
		FIELD_FLIP_EN				= BITS(2:2),	// 	 Flip the fields
		FIELD_FORCE_EN				= BITS(3:3),	//   Force field number
		VSYNC_WINDOW_EN				= BITS(4:4),	//   Enable VSYNC window

	VIP_VS_FRAME_TOTAL				= 0x0550,
		VS_FRAME_TOTAL				= BITS(9:0),	// number of lines per frame

	VIP_VS_LINE_COUNT				= 0x0554,
		VS_LINE_COUNT				= BITS(9:0),	// current line counter
		VS_ITU656_VB				= BITS(13:13),
		VS_ITU656_FID				= BITS(14:14),
		VS_INTERLACE_DETECTED		= BITS(15:15),
		VS_DETECTED_LINES			= BITS(25:16),	// detected number of lines per frame
		CURRENT_FIELD				= BITS(27:27),	// current field number (odd or even)
		PREVIOUS_FIELD				= BITS(28:28),	// previous field number (odd or even)
		ARTIFICIAL_FIELD			= BITS(29:29),
		VS_WINDOW_COUNT				= BITS(31:30),

	// Video Decoder Chroma Processor
	VIP_CP_PLL_CNTL0				= 0x0580,
		CH_DTO_INC					= BITS(23:0),
		CH_PLL_SGAIN				= BITS(27:24),
		CH_PLL_FGAIN				= BITS(31:28),

	VIP_CP_PLL_CNTL1				= 0x0584,
		VFIR						= BITS(0:0),	// 0=disable, 1=enable phase filter FIR
		PFLIP						= BITS(1:1),	// 0=Use PAL/SECAM Vswitch as detected
													// 1=Flip detected PAL/SECAM Vswitch
		PFILT						= BITS(2:2),	// 0=Use sign bit of phase error for PAL Vswitch
													// 1=Use PAL Vswitch filter

	VIP_CP_HUE_CNTL					= 0x0588,
		HUE_ADJ						= BITS(7:0),	// Hue adjustment

	VIP_CP_BURST_GAIN				= 0x058c,
		CR_BURST_GAIN				= BITS(8:0),
		CB_BURST_GAIN				= BITS(24:16),

	VIP_CP_AGC_CNTL					= 0x0590,
		CH_HEIGHT					= BITS(7:0),
		CH_KILL_LEVEL				= BITS(15:8),
		CH_AGC_ERROR_LIM			= BITS(17:16),	// Force error to 0, 1, 2 or 3
		CH_AGC_FILTER_EN			= BITS(18:18),	// 0=disable, 1=enable filter
		CH_AGC_LOOP_SPEED			= BITS(19:19),	// 0=slow, 1=fast

	VIP_CP_ACTIVE_GAIN				= 0x0594,
		CRDR_ACTIVE_GAIN			= BITS(9:0),	// Saturation adjustment
		CBDB_ACTIVE_GAIN			= BITS(25:16),

	VIP_CP_PLL_STATUS0				= 0x0598,
		CH_GAIN_ACC0				= BITS(13:0),
		CH_GAIN_ACC1				= BITS(29:16),

	VIP_CP_PLL_STATUS1				= 0x059c,
		CH_VINT_OUT					= BITS(18:0),

	VIP_CP_PLL_STATUS2				= 0x05a0,
		CH_UINT_OUT					= BITS(12:0),
		CH_VSWITCH					= BITS(16:16),
		CH_SECAM_SWITCH				= BITS(17:17),
		CH_PAL_SWITCH				= BITS(18:18),
		CH_PAL_FLT_STAT				= BITS(21:19),
		CH_COLOR_KILL				= BITS(22:22),

	VIP_CP_PLL_STATUS3				= 0x05a4,
		CH_ERROR_INT0				= BITS(20:0),

	VIP_CP_PLL_STATUS4				= 0x05a8,
		CH_ERROR_INT1				= BITS(20:0),

	VIP_CP_PLL_STATUS5				= 0x05ac,
		CH_FAST_PATH				= BITS(24:0),

	VIP_CP_PLL_STATUS6				= 0x05b0,
		CH_SLOW_PATH				= BITS(24:0),

	VIP_CP_PLL_STATUS7				= 0x05b4,
		FIELD_BPHASE_COUNT			= BITS(5:0),
		BPHASE_BURST_COUNT			= BITS(13:8),

	VIP_CP_DEBUG_FORCE				= 0x05b8,
		GAIN_FORCE_DATA				= BITS(11:0),
		GAIN_FORCE_EN				= BITS(12:12),	// 0=disable, 1==enable force chroma gain

	VIP_CP_VERT_LOCKOUT				= 0x05bc,
		CP_LOCKOUT_START			= BITS(9:0),
		CP_LOCKOUT_END				= BITS(25:16),

	// Video Decoder Clip Engine and VBI Control
	VIP_H_ACTIVE_WINDOW				= 0x05c0,
		H_ACTIVE_START				= BITS(10:0),	// Horizotal active window
		H_ACTIVE_END				= BITS(26:16),

	VIP_V_ACTIVE_WINDOW				= 0x05c4,
		V_ACTIVE_START				= BITS(9:0),	// Vertical active window
		V_ACTIVE_END				= BITS(25:16),

	VIP_H_VBI_WINDOW				= 0x05c8,
		H_VBI_WIND_START			= BITS(10:0),	// Horizontal VBI window
		H_VBI_WIND_END				= BITS(26:16),

	VIP_V_VBI_WINDOW				= 0x05cc,
		V_VBI_WIND_START			= BITS(9:0),	// Vertical VBI window
		V_VBI_WIND_END				= BITS(25:16),

	VIP_VBI_CONTROL					= 0x05d0,
		VBI_CAPTURE_ENABLE			= BITS(1:0),	// Select VBI capture
			VBI_CAPTURE_DIS			= 0 << 0,		//   Disable VBI capture
			VBI_CAPTURE_EN			= 1 << 0,		//   Enable VBI capture
			VBI_CAPTURE_RAW			= 2 << 0,		//   Enable Raw Video capture


	// Video Decoder Standard
	VIP_STANDARD_SELECT				= 0x0408,
		STANDARD_SEL				= BITS(1:0),	// Select video standard
			STANDARD_NTSC			= 0 << 0,		//   NTSC
			STANDARD_PAL			= 1 << 0,		//   PAL
			STANDARD_SECAM			= 2 << 0,		//   SECAM
		YC_MODE						= BITS(2:2),	// Select YC video mode
			YC_MODE_COMPOSITE		= 0 << 2,		//   Composite
			YC_MODE_SVIDEO			= 1 << 2,		//   SVideo

	// Video In Scaler and DVS Port
	VIP_SCALER_IN_WINDOW			= 0x0618,		// Scaler In Window
		H_IN_WIND_START				= BITS(10:0),	//   Horizontal start
		V_IN_WIND_START				= BITS(25:16),	//   Vertical start

	VIP_SCALER_OUT_WINDOW			= 0x061c,		// Scaler Out Window
		H_OUT_WIND_WIDTH			= BITS(9:0),	//   Horizontal output window width
		V_OUT_WIND_HEIGHT			= BITS(24:16),	//   Vertical output window height

	VIP_H_SCALER_CONTROL			= 0x0600,		// Horizontal Scaler control
		H_SCALE_RATIO				= BITS(20:0),	//   Horizontal scale ratio (5.16 fixed point)
		H_SHARPNESS					= BITS(28:25),	//   Sharpness control (15=6dB high frequency boost)
		H_BYPASS					= BITS(30:30),	//   Horizontal bypass enable

	VIP_V_SCALER_CONTROL			= 0x0604,		// Vertical Scaler control
		V_SCALE_RATIO				= BITS(11:0),	//   Vertical scaling ratio (1.11 fixed point)
		V_DEINTERLACE_ON			= BITS(12:12),	//   Enable deinterlacing
		V_FIELD_FLIP				= BITS(13:13),	//   Invert field flag
		V_BYPASS					= BITS(14:14),	//   Enable vertical bypass
		V_DITHER_ON					= BITS(15:15),	//   Vertical path dither enable

	VIP_V_DEINTERLACE_CONTROL		= 0x0608,		// Deinterlace control
		EVENF_OFFSET				= BITS(10:0),	//   Even Field offset
		ODDF_OFFSET					= BITS(21:11),	//   Odd Field offset

	VIP_VBI_SCALER_CONTROL			= 0x060c,		// VBI Scaler control
		VBI_SCALING_RATIO			= BITS(16:0),	//   Scaling ratio for VBI data (1.16 fixed point)
		VBI_ALIGNER_ENABLE			= BITS(17:17),	//   VBI/Raw data aligner enable

	VIP_DVS_PORT_CTRL				= 0x0610,		// DVS Port control
		DVS_DIRECTION				= BITS(0:0),	//   DVS direction
			DVS_DIRECTION_INPUT		= 0 << 0,		//     Input mode
			DVS_DIRECTION_OUTPUT	= 1 << 0,		//     Output mode
		DVS_VBI_BYTE_SWAP			= BITS(1:1),	//   Output video stream type
			DVS_VBI_BYTE_SEQUENTIAL	= 0 << 1,		//     Sequential
			DVS_VBI_BYTE_SWAPPED	= 1 << 1,		//     Byte swapped
		DVS_CLK_SELECT				= BITS(2:2),	//   DVS output clock select
			DVS_CLK_SELECT_8X		= 0 << 2,		//     8x Fsc
			DVS_CLK_SELECT_27MHz	= 1 << 2,		//     27 MHz
		CONTINUOUS_STREAM			= BITS(3:3),	//   Enable continuous stream mode
		DVSOUT_CLK_DRV				= BITS(4:4),	// 0=high, 1=low DVS port output clock buffer drive strength
		DVSOUT_DATA_DRV				= BITS(5:5),	// 0=high, 1=low DVS port output data buffers driver strength

	VIP_DVS_PORT_READBACK			= 0x0614,		// DVS Port readback
		DVS_OUTPUT_READBACK			= BITS(7:0),	//   Data from DVS port fifo

	// Clock and Reset Control
	VIP_CLKOUT_GPIO_CNTL			= 0x0038,
		CLKOUT0_SEL					= BITS(2:0),	// Select output to CLKOUT0_GPIO0 pin
			CLKOUT0_SEL_REF_CLK		= 0 << 0,		//   Reference Clock
			CLKOUT0_SEL_L54_CLK		= 1 << 0,		//   Lockable 54 MHz Clock
			CLKOUT0_SEL_AUD_CLK		= 2 << 0,		//   Audio Source Clock
			CLKOUT0_SEL_DIV_AUD_CLK	= 3 << 0,		//   Divided Audio Source Clock
			CLKOUT0_SEL_BYTE_CLK	= 4 << 0,		//   Byte Clock
			CLKOUT0_SEL_PIXEL_CLK	= 5 << 0,		//   Pixel Clock
			CLKOUT0_SEL_TEST_MUX	= 6 << 0,		//   Clock Test Mux Output
			CLKOUT0_SEL_GPIO0_OUT	= 7 << 0,		//   GPIO0_OUT
		CLKOUT0_DRV					= BITS(3:3),	// Set drive strength for CLKOUT0_GPIO0 pin
			CLKOUT0_DRV_8mA			= 0 << 3,		//   8 mA
			CLKOUT0_DRV_4mA			= 1 << 3,		//   4 mA
		CLKOUT1_SEL					= BITS(6:4),	// Select output to CLKOUT1_GPIO1 pin
			CLKOUT1_SEL_REF_CLK		= 0 << 4,		//   Reference Clock
			CLKOUT1_SEL_L54_CLK		= 1 << 4,		//   Lockable 54 MHz Clock
			CLKOUT1_SEL_AUD_CLK		= 2 << 4,		//   Audio Source Clock
			CLKOUT1_SEL_DIV_AUD_CLK	= 3 << 4,		//   Divided Audio Source Clock
			CLKOUT1_SEL_PIXEL_CLK	= 4 << 4,		//   Pixel Clock
			CLKOUT1_SEL_SPDIF_CLK	= 5 << 4,		//   SPDIF Clock
			CLKOUT1_SEL_REG_CLK		= 6 << 4,		//   Register Clock
			CLKOUT1_SEL_GPIO1_OUT	= 7 << 4,		//   GPIO1_OUT
		CLKOUT1_DRV					= BITS(7:7),	// Set drive strength for CLKOUT1_GPIO1 pin
			CLKOUT1_DRV_8mA			= 0 << 7,		//   8 mA
			CLKOUT1_DRV_4mA			= 1 << 7,		//   4 mA
		CLKOUT2_SEL					= BITS(10:8),	// Select output to CLKOUT2_GPIO2 pin
			CLKOUT2_SEL_REF_CLK		= 0 << 0,		//   Reference Clock
			CLKOUT2_SEL_L54_CLK		= 1 << 0,		//   Lockable 54 MHz Clock
			CLKOUT2_SEL_AUD_CLK		= 2 << 0,		//   Audio Source Clock
			CLKOUT2_SEL_DIV_AUD_CLK	= 3 << 0,		//   Divided Audio Source Clock
			CLKOUT2_SEL_VIN_CLK		= 4 << 0,		//   Video In Clock
			CLKOUT2_SEL_VIN_SC_CLK	= 5 << 0,		//   Video In Scaler Clock
			CLKOUT2_SEL_TV_CLK		= 6 << 0,		//   TV Clock