📄 radeon.h
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#define VERT_FP_LOOP_STRETCH (0x7 << 28)#define VERT_STRETCH_RESERVED 0xf1000000/* DAC_CNTL bit constants */ #define DAC_8BIT_EN 0x00000100#define DAC_4BPP_PIX_ORDER 0x00000200#define DAC_CRC_EN 0x00080000#define DAC_MASK_ALL (0xff << 24)#define DAC_EXPAND_MODE (1 << 14)#define DAC_VGA_ADR_EN (1 << 13)#define DAC_RANGE_CNTL (3 << 0)#define DAC_BLANKING (1 << 2)#define DAC_CMP_EN (1 << 3)/* DAC_CNTL2 bit constants */ #define DAC2_CMP_EN (1 << 7)/* GEN_RESET_CNTL bit constants */#define SOFT_RESET_GUI 0x00000001#define SOFT_RESET_VCLK 0x00000100#define SOFT_RESET_PCLK 0x00000200#define SOFT_RESET_ECP 0x00000400#define SOFT_RESET_DISPENG_XCLK 0x00000800/* MEM_CNTL bit constants */#define MEM_CTLR_STATUS_IDLE 0x00000000#define MEM_CTLR_STATUS_BUSY 0x00100000#define MEM_SEQNCR_STATUS_IDLE 0x00000000#define MEM_SEQNCR_STATUS_BUSY 0x00200000#define MEM_ARBITER_STATUS_IDLE 0x00000000#define MEM_ARBITER_STATUS_BUSY 0x00400000#define MEM_REQ_UNLOCK 0x00000000#define MEM_REQ_LOCK 0x00800000/* RBBM_SOFT_RESET bit constants */#define SOFT_RESET_CP (1 << 0)#define SOFT_RESET_HI (1 << 1)#define SOFT_RESET_SE (1 << 2)#define SOFT_RESET_RE (1 << 3)#define SOFT_RESET_PP (1 << 4)#define SOFT_RESET_E2 (1 << 5)#define SOFT_RESET_RB (1 << 6)#define SOFT_RESET_HDP (1 << 7)/* SURFACE_CNTL bit consants */#define SURF_TRANSLATION_DIS (1 << 8)#define NONSURF_AP0_SWP_16BPP (1 << 20)#define NONSURF_AP0_SWP_32BPP (1 << 21)#define NONSURF_AP1_SWP_16BPP (1 << 22)#define NONSURF_AP1_SWP_32BPP (1 << 23)/* DEFAULT_SC_BOTTOM_RIGHT bit constants */#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)/* MM_INDEX bit constants */#define MM_APER 0x80000000/* CLR_CMP_CNTL bit constants */#define COMPARE_SRC_FALSE 0x00000000#define COMPARE_SRC_TRUE 0x00000001#define COMPARE_SRC_NOT_EQUAL 0x00000004#define COMPARE_SRC_EQUAL 0x00000005#define COMPARE_SRC_EQUAL_FLIP 0x00000007#define COMPARE_DST_FALSE 0x00000000#define COMPARE_DST_TRUE 0x00000100#define COMPARE_DST_NOT_EQUAL 0x00000400#define COMPARE_DST_EQUAL 0x00000500#define COMPARE_DESTINATION 0x00000000#define COMPARE_SOURCE 0x01000000#define COMPARE_SRC_AND_DST 0x02000000/* DP_CNTL bit constants */#define DST_X_RIGHT_TO_LEFT 0x00000000#define DST_X_LEFT_TO_RIGHT 0x00000001#define DST_Y_BOTTOM_TO_TOP 0x00000000#define DST_Y_TOP_TO_BOTTOM 0x00000002#define DST_X_MAJOR 0x00000000#define DST_Y_MAJOR 0x00000004#define DST_X_TILE 0x00000008#define DST_Y_TILE 0x00000010#define DST_LAST_PEL 0x00000020#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080#define DST_BRES_SIGN 0x00000100#define DST_HOST_BIG_ENDIAN_EN 0x00000200#define DST_POLYLINE_NONLAST 0x00008000#define DST_RASTER_STALL 0x00010000#define DST_POLY_EDGE 0x00040000/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */#define DST_X_MAJOR_S 0x00000000#define DST_Y_MAJOR_S 0x00000001#define DST_Y_BOTTOM_TO_TOP_S 0x00000000#define DST_Y_TOP_TO_BOTTOM_S 0x00008000#define DST_X_RIGHT_TO_LEFT_S 0x00000000#define DST_X_LEFT_TO_RIGHT_S 0x80000000/* DP_DATATYPE bit constants */#define DST_8BPP 0x00000002#define DST_15BPP 0x00000003#define DST_16BPP 0x00000004#define DST_24BPP 0x00000005#define DST_32BPP 0x00000006#define DST_8BPP_RGB332 0x00000007#define DST_8BPP_Y8 0x00000008#define DST_8BPP_RGB8 0x00000009#define DST_16BPP_VYUY422 0x0000000b#define DST_16BPP_YVYU422 0x0000000c#define DST_32BPP_AYUV444 0x0000000e#define DST_16BPP_ARGB4444 0x0000000f#define BRUSH_SOLIDCOLOR 0x00000d00#define SRC_MONO 0x00000000#define SRC_MONO_LBKGD 0x00010000#define SRC_DSTCOLOR 0x00030000#define BYTE_ORDER_MSB_TO_LSB 0x00000000#define BYTE_ORDER_LSB_TO_MSB 0x40000000#define DP_CONVERSION_TEMP 0x80000000#define HOST_BIG_ENDIAN_EN (1 << 29)/* DP_GUI_MASTER_CNTL bit constants */#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002#define GMC_SRC_CLIP_DEFAULT 0x00000000#define GMC_SRC_CLIP_LEAVE 0x00000004#define GMC_DST_CLIP_DEFAULT 0x00000000#define GMC_DST_CLIP_LEAVE 0x00000008#define GMC_BRUSH_8x8MONO 0x00000000#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010#define GMC_BRUSH_8x1MONO 0x00000020#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030#define GMC_BRUSH_1x8MONO 0x00000040#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050#define GMC_BRUSH_32x1MONO 0x00000060#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070#define GMC_BRUSH_32x32MONO 0x00000080#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090#define GMC_BRUSH_8x8COLOR 0x000000a0#define GMC_BRUSH_8x1COLOR 0x000000b0#define GMC_BRUSH_1x8COLOR 0x000000c0#define GMC_BRUSH_SOLID_COLOR 0x000000d0#define GMC_DST_8BPP 0x00000200#define GMC_DST_15BPP 0x00000300#define GMC_DST_16BPP 0x00000400#define GMC_DST_24BPP 0x00000500#define GMC_DST_32BPP 0x00000600#define GMC_DST_8BPP_RGB332 0x00000700#define GMC_DST_8BPP_Y8 0x00000800#define GMC_DST_8BPP_RGB8 0x00000900#define GMC_DST_16BPP_VYUY422 0x00000b00#define GMC_DST_16BPP_YVYU422 0x00000c00#define GMC_DST_32BPP_AYUV444 0x00000e00#define GMC_DST_16BPP_ARGB4444 0x00000f00#define GMC_SRC_MONO 0x00000000#define GMC_SRC_MONO_LBKGD 0x00001000#define GMC_SRC_DSTCOLOR 0x00003000#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000#define GMC_DP_CONVERSION_TEMP_9300 0x00008000#define GMC_DP_CONVERSION_TEMP_6500 0x00000000#define GMC_DP_SRC_RECT 0x02000000#define GMC_DP_SRC_HOST 0x03000000#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000#define GMC_3D_FCN_EN_CLR 0x00000000#define GMC_3D_FCN_EN_SET 0x08000000#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000#define GMC_AUX_CLIP_LEAVE 0x00000000#define GMC_AUX_CLIP_CLEAR 0x20000000#define GMC_WRITE_MASK_LEAVE 0x00000000#define GMC_WRITE_MASK_SET 0x40000000#define GMC_CLR_CMP_CNTL_DIS (1 << 28)#define GMC_SRC_DATATYPE_COLOR (3 << 12)#define ROP3_S 0x00cc0000#define ROP3_SRCCOPY 0x00cc0000#define ROP3_P 0x00f00000#define ROP3_PATCOPY 0x00f00000#define DP_SRC_SOURCE_MASK (7 << 24)#define GMC_BRUSH_NONE (15 << 4)#define DP_SRC_SOURCE_MEMORY (2 << 24)#define GMC_BRUSH_SOLIDCOLOR 0x000000d0/* DP_MIX bit constants */#define DP_SRC_RECT 0x00000200#define DP_SRC_HOST 0x00000300#define DP_SRC_HOST_BYTEALIGN 0x00000400/* MPLL_CNTL bit constants */#define MPLL_RESET 0x00000001/* MDLL_CKO bit constants */#define MCKOA_SLEEP 0x00000001#define MCKOA_RESET 0x00000002#define MCKOA_REF_SKEW_MASK 0x00000700#define MCKOA_FB_SKEW_MASK 0x00007000/* MDLL_RDCKA bit constants */#define MRDCKA0_SLEEP 0x00000001#define MRDCKA0_RESET 0x00000002#define MRDCKA1_SLEEP 0x00010000#define MRDCKA1_RESET 0x00020000/* VCLK_ECP_CNTL constants */#define PIXCLK_ALWAYS_ONb 0x00000040#define PIXCLK_DAC_ALWAYS_ONb 0x00000080/* BUS_CNTL1 constants */#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26#define BUS_CNTL1_AGPCLK_VALID 0x80000000/* PLL_PWRMGT_CNTL constants */#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000/* TV_DAC_CNTL constants */#define TV_DAC_CNTL_BGSLEEP 0x00000040#define TV_DAC_CNTL_DETECT 0x00000010#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000#define TV_DAC_CNTL_BGADJ__SHIFT 16#define TV_DAC_CNTL_DACADJ__SHIFT 20#define TV_DAC_CNTL_RDACPD 0x01000000#define TV_DAC_CNTL_GDACPD 0x02000000#define TV_DAC_CNTL_BDACPD 0x04000000/* DISP_MISC_CNTL constants */#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)/* DISP_PWR_MAN constants */#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)#define DISP_PWR_MAN_DISP_D3_RST (1 << 16)#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)/* masks */#define CONFIG_MEMSIZE_MASK 0x1f000000#define MEM_CFG_TYPE 0x40000000#define DST_OFFSET_MASK 0x003fffff#define DST_PITCH_MASK 0x3fc00000#define DEFAULT_TILE_MASK 0xc0000000#define PPLL_DIV_SEL_MASK 0x00000300#define PPLL_RESET 0x00000001#define PPLL_ATOMIC_UPDATE_EN 0x00010000#define PPLL_REF_DIV_MASK 0x000003ff#define PPLL_FB3_DIV_MASK 0x000007ff#define PPLL_POST3_DIV_MASK 0x00070000#define PPLL_ATOMIC_UPDATE_R 0x00008000#define PPLL_ATOMIC_UPDATE_W 0x00008000#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000#define GUI_ACTIVE 0x80000000#endif /* _RADEON_H */⌨️ 快捷键说明
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