sisoutputreader.java~

Java遗传算法库

                        M[ ml ] = false;
                    }
                }
                //System.out.println("M=" + es.ESLib.boolArr2String( M )); //D
            }
            for( int ml = 0; ml < inputCombs; ml++ )
            {
                if( M[ ml ] )
                {
                    rv[ ml ] = true;
                }
            }
        }
        
        return rv;
    }
    
    /** @param pin What String we are looking for.
     * @param hay Where to look for it.
     * @return Lowest index i at which hay[ i ].equals( pin ) is true, or -1 if always false.
     */ // Tested 17-07-03
    public static int indexOf( String pin, String[] hay )
    {
        for( int ol = 0; ol < hay.length; ol++ )
        {
            if( pin.equals( hay[ ol ] ) )
            {
                return ol;
            }
        }
        return -1;
    }

    /** Find a unit by its name
     */ // Tested 17-07-03
    static SimulatorLogicElement getByName( Vector els, Hashtable codes, String name )
    {
        SimulatorLogicElement rv;
        int iix = 0;
        if( name != null )
        {
            Object oix = codes.get( name );
            Integer Ix = ( Integer ) codes.get( name );
            iix = Ix.intValue();
        }
        return ( SimulatorLogicElement )els.get( iix );
    }
    

    static class TwoLUTEdgeDLatch
    {
        Vector els;
        Hashtable codes;

        final boolean[] orTable = { f, t, t, t };
        final boolean[] andTable = {f, f, f, t };
        final boolean[] andNATable = {f, t, f, f};

        SimulatorLUT e0 = new SimulatorLUT( orTable, DEF_DELAY );
        SimulatorLUT e1 = new SimulatorLUT( andTable, DEF_DELAY );
        SimulatorLUT e2 = new SimulatorLUT( andNATable, DEF_DELAY );
        SimulatorLUT e3 = new SimulatorLUT( orTable, DEF_DELAY );
        SimulatorLUT e4 = new SimulatorLUT( andNATable, DEF_DELAY );

        SimulatorLUT[] latchEls = { e0,e1,e2,e3,e4 };

        public TwoLUTEdgeDLatch( Vector els, Hashtable codes )
        {
            this.els = els;
            this.codes = codes;

            SimulatorLogicElement C = getByName( els, codes, "C" );

            SimulatorLogicElement[] c0 = { e1, e2 };
            SimulatorLogicElement[] c1 = { e3, C };
            SimulatorLogicElement[] c2 = { C, e0 };
            SimulatorLogicElement[] c3 = { e1, e4 };
            SimulatorLogicElement[] c4 = { C, null };
            SimulatorLogicElement[][] connects = { c0,c1,c2,c3,c4 };

            for( int ll = 0; ll < LUT2_LATCH_SIZE; ll++ )
            {
                SimulatorLogicElement[] currConnects = connects[ ll ];
                latchEls[ ll ].connect( currConnects );
                //System.out.println("connecting latch el " + ll + " to " + currConnects[ 0 ] + "," + currConnects[ 1 ] );
            }
            
            
        }

        public void putInVector( int pos )
        {
            for( int ll = 0; ll < LUT2_LATCH_SIZE; ll++ )
            {
                els.set( pos++, latchEls[ ll ] );
            }
        }

        public void connectInput( SimulatorLogicElement D )
        {
            //System.out.println("connectin");
            //System.out.println( e4 );
            SimulatorLogicElement[] c4 = e4.getInputs();
            c4[ 1 ] = D;
            e4.connect( c4 );
        }
    }

    public static String vector2Gene( Vector added, SimulatorLogicElement[] globIns, int bitsPerVar, int lutInputs, boolean varSized )
    {
        //System.out.println("Vector2Gene GI=" + globIns.length + "ADDS="+added.size());//debug
        int totAddEls = 1 << bitsPerVar;
        String gene = "";
        int lutLength = 1 << lutInputs;
        String emptyGene = ESLib.int2BinStr( 0, lutLength );
        for( int il = 0; il < lutInputs; il++ )
        {
            emptyGene += ESLib.int2BinStr( 0, bitsPerVar );
        }
        
        int startAt, endAt;
        if( varSized )
        {
            startAt = globIns.length;
            endAt = added.size();
        }else
        {
            startAt = 0;
            endAt = added.size() - globIns.length;
        }
        for( int al = startAt; al < endAt; al++ )
        {
            SimulatorLogicElement el = ( SimulatorLogicElement ) added.get( al );
            if( el == null )
            {
                gene += emptyGene;
            }else
            {
                gene += el;
                SimulatorLogicElement[] ins = el.getInputs();
                //System.out.println("el " + al + "=" + el ); //debug
                for( int il = 0; il < ins.length; il++ )
                {
                    gene += ESLib.int2BinStr(added.indexOf( ins[ il ] ), bitsPerVar);
                }
            }
            //System.out.println("Loop " + al + " rrv size " + gene.length());//debug
        }
        return gene;
    }        
    
    
    public static String vector2FPGAGene( Vector added, SimulatorLogicElement[] globIns, int bitsPerVar, int lutInputs, int nrOuts, boolean varSized, int reservedOutputs, int nrLUTs )
    {
        //System.out.println("Vector2Gene GI=" + globIns.length + "ADDS="+added.size());//debug
        
        // Blocks contain LUT and Latch
        // Elements are anything
        
        String gene = "";
        int blockBPV = bitsPerVar;          int totAddBlocks = 1 << blockBPV;
        int elementBPV = bitsPerVar + 1;    int totAddElements = 1 << elementBPV;
        int lutLength = 1 << lutInputs;     int nrIns = globIns.length;
        String emptyLUTGene = ESLib.int2BinStr( 0, lutLength );
        
        // 0. Output defs, point to CLBs 0,1,..,q-1
        for( int ol = 0; ol < nrOuts - reservedOutputs; ol++ )
        {
            int currOutputAdd = varSized ? ol + nrIns : ol;
            gene += ESLib.int2BinStr( currOutputAdd, elementBPV );
        }
        // 0.1 Reserved Outputs don't have specially reserved LUT, they point to evolvable stuff.
        for( int ol = 0; ol < reservedOutputs; ol++ )
        {
            int currOutputAdd = varSized ? nrLUTs + ol + nrIns : nrLUTs + ol;
            gene += ESLib.int2BinStr( currOutputAdd, elementBPV );
        }
        for( int il = 0; il < lutInputs; il++ )
        {
            emptyLUTGene += ESLib.int2BinStr( 0, elementBPV ); // Need all bits for addresses
        }
        String emptyEDLGene = ESLib.int2BinStr( 0, elementBPV ); // One extra input for Latch
        int startAt, endAt;
        if( varSized )
        {
            startAt = nrIns;
            endAt = added.size() / 2;
        }else
        {
            startAt = 0;
            endAt = added.size() / 2 - nrIns;
        }
         
        for( int al = startAt; al < endAt; al++ ) // Only Loop for LUTs, will do Latches within loop
        {
            SimulatorLogicElement LUTel = ( SimulatorLogicElement ) added.get( al );
            SimulatorEdgeDLatch EDLel = ( SimulatorEdgeDLatch ) added.get( al + totAddBlocks );
            String currGene="";//d
            // First do LUT gene bit
            if( LUTel == null )
            {
                gene += emptyLUTGene;
                currGene = emptyLUTGene; //d
            }else
            {
                gene += LUTel; // Table itself
                currGene += LUTel;
                SimulatorLogicElement[] ins = LUTel.getInputs();
                //System.out.println("el " + al + "=" + el ); //debug
                for( int il = 0; il < ins.length; il++ )
                {
                    gene += ESLib.int2BinStr(added.indexOf( ins[ il ] ), elementBPV );
                }
            }
            // Now do EDL input
            if( EDLel == null )
            {
                gene += emptyEDLGene;
            }else
            {
                SimulatorLogicElement[] ins = EDLel.getInputs();
                gene += ESLib.int2BinStr(added.indexOf( ins[ EDLel.D ] ), elementBPV );
            }
            //System.out.println("Loop " + al + " rrv size " + gene.length());//debug
        }
        return gene;
    }

    protected static int whatInput( SimulatorLogicElement el, SimulatorLogicElement[] inputs )
    {
        int rv = -1;
        for( int il = 0; il < inputs.length; il++ )
        {
            if( inputs[ il ] == el )
            {
                rv = il;
            }
        }
        return rv;
    }
    
    public String getVassilevGenotype()
    {
        String source = getGenotype();
        int bpev = bitsPerVar;
        int nrOutputs = totalOutputs;
        int lutIns = lutInputs;
        if( FPGALUT )
        {
            return FPGALUT2VassLUT( source, bpev, nrOutputs, lutIns );
        }else
        {
            return LUT2VassLUT( source, bpev, nrOutputs );
        }
    }
    
    protected static String LUT2VassLUT( String source, int bpv, int nrOutputs )
    {
        String outDef = "";
        for( int ql = 0; ql < nrOutputs; ql++ )
        {
            outDef += ESLib.int2BinStr( ql, bpv );
        }
        return outDef + source;
    }
    
    /** Assumes circuit has no latches.  Converts from FPGALUT genotype to VassilevLUT */
    protected static String FPGALUT2VassLUT( String source, int bpb, int nrOutputs, int lutIns )
    {
        int lutSize = 1 << lutIns;        
        int bpae = bpb + 1;
        String dest = "";
        int ix = 0;
        for( int ql = 0; ql < nrOutputs; ql++ )
        {
            dest += source.substring( ix + 1, ix + bpae );
            ix += bpae;
        }
        while( ix + lutSize < source.length() )
        {
            dest += source.substring( ix, ix + lutSize );
            ix += lutSize;
            for( int ll = 0; ll < lutIns; ll++ )
            {
                dest += source.substring( ix + 1, ix + bpae );
                ix += bpae;
            }
            ix += bpae; // for latch input
        }
        return dest;
    }
    
    public String getGenotype()
    {
        return genotype;
    }
    
    public int getBitsPerVar()
    {
        return bitsPerVar;
    }
    
    public int getTotalEls()
    {
        return totalEls;
    }
}