📄 sisoutputreader.java~
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/*
* SisOutputReader.java
*
* Created on May 29, 2003, 12:26 PM
*/
package es.pj.circuits.fpgaft;
import es.BitSet;
import es.ESLib;
import es.pj.circuits.SimulatorLogicElement;
import es.pj.circuits.SimulatorDelayLE;
import java.util.Vector;
import java.util.Hashtable;
import java.util.StringTokenizer;
import java.io.BufferedReader;
import java.io.StringReader;
import java.io.FileReader;
import java.io.IOException;
import java.io.File;
/** Constructed with the output from the logic optimizer Sis, it will build a genotype to be mapped
* with the LUTAbsoluteMapping into a circuit. The circuit must be mapped using the xl_* commands
* from Sis which use LUT + Latch technology. Then it must be printed using the commands
* print_io, print, print_latch in that order. This must be put into a file which is given to this class.
*
* @author Michael Garvie
* @version
*/
public class SisOutputReader extends Object {
// Constants
public final static int DEF_DELAY = 0;
public final static int LUT2_LATCH_SIZE = 5;
public final static int DEFAULT_LUT_SIZE = 2;
public final static int DEFAULT_RESERVED_OUTPUTS = 0;
public final static boolean DEFAULT_FPGA_MAPPING = false;
public final static boolean DEFAULT_SPACE_FOR_VOTER = false;
// Sis Output structure constants
public final static String SIS_DELIMETERS = "[]{}'= +";
public final static String LATCH_DEF_START_TOKEN = "input: ";
public final static String LATCH_INPUT_DEF_TOKEN = "input:";
public final static String LATCH_OUTPUT_DEF_TOKEN = "output:";
public final static String INPUT_DEF_START_TOKEN = "primary inputs: ";
public final static String OUTPUT_DEF_START_TOKEN = "primary outputs: ";
public final static String ELEMENT_DEF_TOKEN = "=";
final static boolean f = false;
final static boolean t = true;
// Mapping Config
protected int lutInputs = DEFAULT_LUT_SIZE;
protected int reservedOutputs = DEFAULT_RESERVED_OUTPUTS;
protected boolean FPGALUT = false;
protected boolean makeSpaceForVoter = false;
protected int extraBitsPerVar = 0;
protected boolean varSized = false;
// Mapping Results
protected String genotype;
protected int bitsPerVar;
protected int totalOutputs;
protected int totalInputs;
protected int totalEls;
/** Number of LUT input defaulted to DEFAULT_LUT_SIZE , mapping defaulted to LUTAbsoluteMapping */
public SisOutputReader( String sisOut ) throws IOException
{
init( sisOut );
}
/** Number of LUT input defaulted to DEFAULT_LUT_SIZE, mapping defaulted to LUTAbsoluteMapping */
public SisOutputReader( File sisOut ) throws IOException
{
this( sisOut, DEFAULT_RESERVED_OUTPUTS, DEFAULT_LUT_SIZE, DEFAULT_FPGA_MAPPING, DEFAULT_SPACE_FOR_VOTER );
}
public SisOutputReader( File sisOut, int resOuts, int lutInputs, boolean FPGALUT, boolean space4Voter, int extraBitsPerVar, boolean varSized ) throws IOException
{
this.varSized = varSized;
this.extraBitsPerVar = extraBitsPerVar;
this.lutInputs = lutInputs;
this.FPGALUT = FPGALUT;
this.makeSpaceForVoter = space4Voter;
reservedOutputs = resOuts;
BufferedReader bur = new BufferedReader( new FileReader( sisOut ) );
String rv = "";
String line;
while( ( line = bur.readLine() ) != null )
{
rv += line + "\n";
}
init( rv );
}
/** @param sisOut File containing output from sis from the commands print and print_latches one after the other.
* @param reservedOutputs Number of outputs to reserve, for eg. for evolving a circuit with BIST.
* @param lutInputs Number of inputs to Look-up Table units.
* @param FPGALUT True if we want the genotype to be usable with the FPGALUTAbsoluteMapping, False to be usable with the LUTAbsoluteMapping
** @param space4Voter True if we want to reserve enough space for two copies of this circuit by increasing the number of addressable units.
*/
public SisOutputReader( File sisOut, int resOuts, int lutInputs, boolean FPGALUT, boolean space4Voter ) throws IOException
{
this.lutInputs = lutInputs;
this.FPGALUT = FPGALUT;
this.makeSpaceForVoter = space4Voter;
reservedOutputs = resOuts;
BufferedReader bur = new BufferedReader( new FileReader( sisOut ) );
String rv = "";
String line;
while( ( line = bur.readLine() ) != null )
{
rv += line + "\n";
}
init( rv );
}
/** Once this method is called (always done by the constructor) the getGenotype() and similar ones
* can be called.
* @param sisOut Output from sis from the commands print and print_latches one after the other.
* @param reservedOutputs Number of outputs to reserve, for eg. for evolving a circuit with BIST.
*/
private void init( String sisOut ) throws IOException
{
// 1-3 Collect I/O & Latch Names
Vector inputNames = new Vector();
Vector outputNames = new Vector();
Vector latchNames = new Vector();
Vector latchInputNames = new Vector();
scan4IOLNames( sisOut, inputNames, outputNames, latchNames, latchInputNames );
// Do some House Work for Sequential Circuits
int reservedInputs = 0;
int totalLatches = latchNames.size();
TwoLUTEdgeDLatch[] LUT2latches = null;
SimulatorEdgeDLatch[] EDLatches = null;
boolean sequential = totalLatches > 0;
if( sequential || FPGALUT )
{
reservedInputs = 1; // For the Clock
}
if( sequential )
{
if( FPGALUT )
{
EDLatches = new SimulatorEdgeDLatch[ totalLatches ];
}else
{
if( lutInputs != 2 )
{
throw new IOException( "Can only generate LUTAbsoluteMapping genotypes for Sequential circuits with 2 input LUTs." );
}
LUT2latches = new TwoLUTEdgeDLatch[ totalLatches ];
}
}
// 4 - Collect Elements
Vector elementNames = scan4ElementNames( sisOut, outputNames );
// 5 - Calculate total number of elements
totalOutputs = outputNames.size();
totalOutputs += reservedOutputs;
totalInputs = inputNames.size() + reservedInputs;
int nrElements = elementNames.size();
int nrAddEls = calcAddEls(FPGALUT, makeSpaceForVoter, outputNames.size(), reservedOutputs, totalInputs, totalLatches, nrElements );
bitsPerVar = calcBitsPerVar( nrAddEls ) + extraBitsPerVar;
//System.out.println("bpv = " + bitsPerVar ); // D
int totalAddLUTs = 1 << bitsPerVar;
int totalAddEls = totalAddLUTs;
totalEls = totalOutputs + nrElements;
if( FPGALUT )
{
totalEls -= reservedOutputs; // These are only forwarding mechanisms
totalAddEls = totalAddLUTs * 2;
}else
{
totalEls += totalLatches * LUT2_LATCH_SIZE;
}
// R - Register Everything
int currIx = 0;
Hashtable codes = new Hashtable();
Vector els = new Vector(); // To set up dummy variables
els.setSize( totalAddEls );
//System.out.println("ELS Size " + els.size() + " =? " + totalAddEls);
// Set up SimulatorLUT objects to be able to point at them before the tables are built
for( int el = 0; el < totalEls; el++ )
{
els.set( el, new SimulatorLUT( new BitSet( 0 ), DEF_DELAY ) ); // has to be there if want to connect to it
//System.out.println("Setting " + el );
}
// 1 - Registed Codes for outputs
for( int ol = 0; ol < totalOutputs - reservedOutputs; ol++, currIx++ )
{
codes.put( outputNames.get( ol ), new Integer( ol ) );
}
// 1.1 - Map reserved outputs to units after all this logic.
SimulatorLUT[] reservedLUTs = new SimulatorLUT[ reservedOutputs ];
if( !FPGALUT )
{
int temp4BufferLUT = 1 << ( lutInputs - 1 );
String bufferLUT = es.ESLib.int2BinStr( ( 1 << temp4BufferLUT ) - 1, 1 << lutInputs ); // 2^(lut ins - 1 ) 0s and then 1s
for( int rl = 0; rl < reservedOutputs; rl++ )
{
//System.out.println( "buff = " + bufferLUT );
reservedLUTs[ rl ] = new SimulatorLUT( new BitSet( bufferLUT ) , DEF_DELAY );
els.set( totalOutputs - rl - 1, reservedLUTs[ rl ] ); // connect later
currIx++;
}
}
// 7 - Codes for inputs
SimulatorLogicElement[] globalIns = new SimulatorLogicElement[ totalInputs ];
for( int il = 0; il < totalInputs - reservedInputs; il++ )
{
codes.put( inputNames.get( il ), new Integer( totalAddLUTs - il - 1 ) );
SimulatorLogicElement currIn = new SimulatorDelayLE( 0 );
els.set( totalAddLUTs - 1 - il, currIn );
globalIns[ il ] = currIn;
}
if( reservedInputs == 1 )
{
codes.put( "C", new Integer( totalAddLUTs - totalInputs ) );
SimulatorLogicElement currIn = new SimulatorDelayLE( 0 );
els.set( totalAddLUTs - totalInputs, currIn );
globalIns[ totalInputs - 1 ] = currIn;
}
// 6 - Codes for latches
for( int ll = 0; ll < totalLatches; ll++ )
{
int latchAddress;
if( FPGALUT )
{
latchAddress = totalAddLUTs + ll;
EDLatches[ ll ] = new SimulatorEdgeDLatch( DEF_DELAY );
//System.out.println("Setting latch at " + latchAddress);
els.set( latchAddress, EDLatches[ ll ] );
}else
{
latchAddress = currIx;
LUT2latches[ ll ] = new TwoLUTEdgeDLatch( els, codes );
LUT2latches[ ll ].putInVector( currIx );
currIx += LUT2_LATCH_SIZE;
}
codes.put( latchNames.get( ll ), new Integer( latchAddress ) );
}
// 8 - Codes for elements
for( int el = 0; el < nrElements; el++, currIx++ )
{
codes.put( elementNames.get( el ), new Integer( currIx ) );
//System.out.println("Putting code " + elementNames.get( el ) + " to " + currIx );
}
// 9 - Scan & Create Elements
BufferedReader bur = new BufferedReader( new StringReader( sisOut ) );
String line;
while( ( line = bur.readLine() ) != null )
{
StringTokenizer stk = new StringTokenizer( line );
if( stk.hasMoreTokens() )
{
stk.nextToken();
if( stk.hasMoreTokens() && stk.nextToken().equals( ELEMENT_DEF_TOKEN ) )
{
addLine( els, codes, line, lutInputs );
}
}
}
// 10 - Connect Latch Inputs
for( int ll = 0; ll < totalLatches; ll++ )
{
SimulatorLogicElement currLatchInput = getByName( els, codes, ( String ) latchInputNames.get( ll ) );
if( FPGALUT )
{
SimulatorLogicElement[] conn = { null, currLatchInput };
EDLatches[ ll ].connect( conn );
}else
{
LUT2latches[ ll ].connectInput( currLatchInput );
}
}
// Make sure reserved outputs point to first non-fixed unit
if( !FPGALUT )
{
for( int rl = 0; rl < reservedOutputs; rl++ )
{
SimulatorLUT fromER = new SimulatorLUT( new BitSet( 1 << lutInputs ) , DEF_DELAY );
els.set( currIx++, fromER );
SimulatorLogicElement[] outERconns = new SimulatorLogicElement[ lutInputs ];
for( int clp = 0; clp < lutInputs; clp++ )
{
outERconns[ clp ] = fromER;
}
reservedLUTs[ rl ].connect( outERconns );
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