h8300.h

cygwin, 著名的在win32下模拟unix操作系统的东东

/* Opcode table for the H8/300
   Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002
   Free Software Foundation, Inc.
   Written by Steve Chamberlain <[e-mail]>.
   
   This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
   
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.
   
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
   
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
   02111-1307, USA.  */

/* Instructions are stored as a sequence of nibbles.
   If the nibble has value 15 or less than the representation is complete.
   Otherwise, we record what it contains with several flags.  */

typedef int op_type;

#define Hex0	0
#define Hex1 	1
#define Hex2 	2
#define Hex3 	3
#define Hex4 	4
#define Hex5 	5
#define Hex6 	6
#define Hex7 	7
#define Hex8 	8
#define Hex9 	9
#define HexA 	10
#define HexB 	11
#define HexC 	12
#define HexD 	13
#define HexE 	14
#define HexF 	15

#define L_8		0x01
#define L_16		0x02
#define L_32		0x04
#define L_P             0x08
#define L_24		0x10
#define MEMRELAX 	0x20			/* move insn which may relax */ 
#define SRC             0x40
#define DST             0x80

#define REG		0x100
#define EXR		0x200
#define MACREG		0x800
#define SRC_IN_DST	0x400
#define IMM		0x1000
#define DISP		0x2000
#define IND		0x4000
#define INC		0x8000
#define DEC		0x10000
#define L_3		0x20000
#define KBIT 		0x40000
#define DBIT            0x80000
#define DISPREG         0x100000
#define IGNORE 		0x200000
#define E      		0x400000		/* FIXME: end of nibble sequence? */
#define L_2		0x800000
#define B30  		0x1000000 		/* bit 3 must be low */
#define B31  		0x2000000		/* bit 3 must be high */
#define CCR		0x4000000
#define ABS             0x8000000
#define ABSJMP		0x10000000  
#define ABS8MEM         0x20000000	
#define PCREL           0x40000000
#define MEMIND          0x80000000

#define IMM3 		IMM|L_3
#define IMM2 		IMM|L_2

#define SIZE		(L_2|L_3|L_8|L_16|L_32|L_P|L_24)
#define MODE		(REG|IMM|DISP|IND|INC|DEC|CCR|ABS|MEMIND|EXR)

#define RD8 		(DST|L_8|REG)
#define RD16 		(DST|L_16|REG)
#define RD32 		(DST|L_32|REG)
#define RS8 		(SRC|L_8|REG)
#define RS16 		(SRC|L_16|REG)
#define RS32		(SRC|L_32|REG)

#define RSP 		(SRC|L_P|REG)
#define RDP 		(DST|L_P|REG)

#define IMM8 		(IMM|SRC|L_8)
#define IMM16 		(IMM|SRC|L_16)
#define IMM32 		(IMM|SRC|L_32)

#define ABS8SRC 	(SRC|ABS|L_8|ABS8MEM)
#define ABS8DST		(DST|ABS|L_8|ABS8MEM)

#define DISP8 		(PCREL|L_8)
#define DISP16 		(PCREL|L_16)

#define DISP8SRC	(DISP|L_8|SRC)
#define DISP16SRC	(DISP|L_16|SRC)

#define DISP8DST	(DISP|L_8|DST)
#define DISP16DST	(DISP|L_16|DST)

#define ABS16SRC 	(SRC|ABS|L_16)
#define ABS16DST 	(DST|ABS|L_16)
#define ABS24SRC 	(SRC|ABS|L_24)
#define ABS24DST 	(DST|ABS|L_24)
#define ABS32SRC 	(SRC|ABS|L_32)
#define ABS32DST 	(DST|ABS|L_32)

#define RDDEC 		(DST|DEC)
#define RSINC 		(SRC|INC)
#define RDINC		(DST|INC)

#define RDIND 		(DST|IND)
#define RSIND 		(SRC|IND)

#if 1
#define OR8 RS8		/* ??? OR as in One Register? */
#define OR16 RS16
#define OR32 RS32
#else
#define OR8 RD8
#define OR16 RD16
#define OR32 RD32
#endif

struct code 
{
  op_type nib[30];
};

struct arg 
{
  op_type nib[3];
};

struct h8_opcode 
{
  int how;
  int inbase;
  int time;
  char *name;
  struct arg args;
  struct code data;
};

#ifdef DEFINE_TABLE

#define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
{ code, 1, 2, name,	{{imm,RD8,E}},	{{op00, op01, imm, RD8, E, 0, 0, 0, 0}}},\
{ code, 1, 6, name,	{{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}},\
{ code, 1, 6, name,	{{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}}\
,{ code, 0, 6, name,	{{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}},\
{ code, 0, 6, name,	{{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}}


#define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
   BITOP(code,imm, name, op00+1, op01, op10,op11, op20,op21,op30),\
   BITOP(code,RS8,  name, op00, op01, op10,op11, op20,op21,op30)

#define WTWOP(code,name, op1, op2) \
{ code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}}

#define BRANCH(code, name, op) \
{ code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}}, \
{ code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}} 

#define SOP(code, x,name) \
{code, 1, x,  name 

#define NEW_SOP(code, in,x,name) \
{code, in, x,  name 
#define EOP  }

#define TWOOP(code, name, op1, op2,op3) \
{ code,1, 2,name, {{IMM8, RD8, E}},	{{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}},\
{ code, 1, 2,name, {{RS8, RD8, E}},	{{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}} 

#define UNOP(code,name, op1, op2) \
{ code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}}

#define UNOP3(code, name, op1, op2, op3) \
{ O(code,SB), 1, 2, name, {{OR8,  E, 0}}, {{op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}}}, \
{ O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}}, \
{ O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}} \
,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST,  E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}}}, \
{ O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}}, \
{ O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}}


#define IMM32LIST IMM32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
#define IMM24LIST IMM24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
#define IMM16LIST IMM16,IGNORE,IGNORE,IGNORE
#define A16LIST L_16,IGNORE,IGNORE,IGNORE
#define DISP24LIST DISP|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
#define DISP32LIST DISP|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
#define ABS24LIST ABS|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
#define ABS32LIST ABS|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
#define A24LIST L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
#define A32LIST L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
#define PREFIX32 0x0,0x1,0x0,0x0
#define PREFIXLDC 0x0,0x1,0x4,0x0


#define O(op, size) (op*4+size)

#define O_RECOMPILE 0
#define O_ADD  1
#define O_ADDX 2
#define O_AND  3
#define O_BAND 4
#define O_BRA  5
#define O_BRN  6
#define O_BHI  7
#define O_BLS  8
#define O_BCC  9
#define O_BCS  10
#define O_BNE  11  
#define O_BVC  12
#define O_BVS  13
#define O_BPL  14
#define O_BMI  15
#define O_BGE  16
#define O_BLT  17
#define O_BGT  18
#define O_BLE  19
#define O_ANDC 20
#define O_BEQ 21
#define O_BCLR 22
#define O_BIAND 23
#define O_BILD 24
#define O_BIOR 25
#define O_BIXOR 26
#define O_BIST 27
#define O_BLD 28
#define O_BNOT 29
#define O_BSET 30
#define O_BSR 31
#define O_BXOR 32
#define O_CMP 33
#define O_DAA 34
#define O_DAS 35
#define O_DEC 36
#define O_DIVU 37
#define O_DIVS 38
#define O_INC 39
#define O_LDC 40
#define O_MOV_TO_MEM 41
#define O_OR 42
#define O_ROTL 43
#define O_ROTR 44
#define O_ROTXL 45
#define O_ROTXR 46
#define O_BPT 47
#define O_SHAL 48
#define O_SHAR 49
#define O_SHLL 50
#define O_SHLR 51
#define O_SUB  52
#define O_SUBS 53
#define O_TRAPA 54
#define O_XOR 55
#define O_XORC 56
#define O_BOR 57
#define O_BST 58
#define O_BTST 59
#define O_EEPMOV 60
#define O_EXTS 61
#define O_EXTU 62
#define O_JMP 63
#define O_JSR 64
#define O_MULU 65
#define O_MULS 66
#define O_NOP 67
#define O_NOT 68
#define O_ORC 69
#define O_RTE 70
#define O_STC 71
#define O_SUBX 72
#define O_NEG 73
#define O_RTS 74
#define O_SLEEP 75
#define O_ILL 76
#define O_ADDS 77
#define O_SYSCALL 78
#define O_MOV_TO_REG 79
#define O_TAS 80
#define O_CLRMAC 82
#define O_LDMAC 83
#define O_MAC 84