startup.lst
来自「cs8900 c51应用」· LST 代码 · 共 631 行 · 第 1/3 页
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A51 MACRO ASSEMBLER STARTUP 11/26/2004 11:32:42 PAGE 1
MACRO ASSEMBLER A51 V7.07
OBJECT MODULE PLACED IN .\8052-obj\Startup.obj
ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE Startup.a51 GEN SET(LARGE,MONITOR) DEBUG PRINT(.\8052-lst\Startup.lst) OBJ
ECT(.\8052-obj\Startup.obj) EP
LOC OBJ LINE SOURCE
1 $nomod51
2 ;------------------------------------------------------------------------------
3 ; This file is part of the C51 Compiler package
4 ; Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc.
5 ;------------------------------------------------------------------------------
6 ; STARTUP.A51: This code is executed after processor reset.
7 ;
8 ; To translate this file use A51 with the following invocation:
9 ;
10 ; A51 STARTUP.A51
11 ;
12 ; To link the modified STARTUP.OBJ file to your application use the following
13 ; BL51 invocation:
14 ;
15 ; BL51 <your object file list>, STARTUP.OBJ <controls>
16 ;
17 ;------------------------------------------------------------------------------
18 ;
19 ; User-defined Power-On Initialization of Memory
20 ;
21 ; With the following EQU statements the initialization of memory
22 ; at processor reset can be defined:
23 ;
24 ; ; the absolute start-address of IDATA memory is always 0
0080 25 IDATALEN EQU 80H ; the length of IDATA memory in bytes.
26 ;
0000 27 XDATASTART EQU 0H ; the absolute start-address of XDATA memory
0000 28 XDATALEN EQU 0H ; the length of XDATA memory in bytes.
29 ;
0000 30 PDATASTART EQU 0H ; the absolute start-address of PDATA memory
0000 31 PDATALEN EQU 0H ; the length of PDATA memory in bytes.
32 ;
33 ; Notes: The IDATA space overlaps physically the DATA and BIT areas of the
34 ; 8051 CPU. At minimum the memory space occupied from the C51
35 ; run-time routines must be set to zero.
36 ;------------------------------------------------------------------------------
37 ;
38 ; Reentrant Stack Initilization
39 ;
40 ; The following EQU statements define the stack pointer for reentrant
41 ; functions and initialized it:
42 ;
43 ; Stack Space for reentrant functions in the SMALL model.
0000 44 IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
0100 45 IBPSTACKTOP EQU 0FFH+1 ; set top of stack to highest location+1.
46 ;
47 ; Stack Space for reentrant functions in the LARGE model.
0001 48 XBPSTACK EQU 1 ; set to 1 if large reentrant is used.
2000 49 XBPSTACKTOP EQU 01FFFH+1; set top of stack to highest location+1.
50 ;
51 ; Stack Space for reentrant functions in the COMPACT model.
0000 52 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
0000 53 PBPSTACKTOP EQU 0FFFFH+1; set top of stack to highest location+1.
54 ;
55 ;------------------------------------------------------------------------------
56 ;
57 ; Page Definition for Using the Compact Model with 64 KByte xdata RAM
A51 MACRO ASSEMBLER STARTUP 11/26/2004 11:32:42 PAGE 2
58 ;
59 ; The following EQU statements define the xdata page used for pdata
60 ; variables. The EQU PPAGE must conform with the PPAGE control used
61 ; in the linker invocation.
62 ;
0000 63 PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
0000 64 PPAGE EQU 0 ; define PPAGE number.
65 ;
66 ;------------------------------------------------------------------------------
67
68 ;#include <at898252.h>
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0080 +1 87 sfr P0 = 0x80; /* Port 0 */
0081 +1 88 sfr SP = 0x81; /* Stack Pointer */
0082 +1 89 sfr DPL = 0x82; /* Data Pointer Low Byte */
0082 +1 90 sfr DP0L = 0x82; /* Alternate Definition */
0083 +1 91 sfr DPH = 0x83; /* Data Pointer High Byte */
0083 +1 92 sfr DP0H = 0x83; /* Alternate Definition */
0084 +1 93 sfr DP1L = 0x84; /* Data Pointer 1 Low Byte , different to AT89C52 */
0085 +1 94 sfr DP1H = 0x85; /* Data Pointer 1 High Byte , different to AT89C52 */
0086 +1 95 sfr SPDR = 0x86; /* SPI Data Register , different to AT89C52 */
0087 +1 96 sfr PCON = 0x87; /* Power Control Register */
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0088 +1 98 sfr TCON = 0x88; /* Timer Control Register */
0089 +1 99 sfr TMOD = 0x89; /* Timer Mode Control Register */
008A +1 100 sfr TL0 = 0x8A; /* Timer 0 Low Byte */
008B +1 101 sfr TL1 = 0x8B; /* Timer 1 Low Byte */
008C +1 102 sfr TH0 = 0x8C; /* Timer 0 High Byte */
008D +1 103 sfr TH1 = 0x8D; /* Timer 1 High Byte */
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0090 +1 105 sfr P1 = 0x90; /* Port 1 */
0096 +1 106 sfr WMCON = 0x96; /* Watchdog and Memory Control Register */
0098 +1 107 sfr SCON = 0x98; /* Serial Port Control */
0099 +1 108 sfr SBUF = 0x99; /* Serial Port Buffer */
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00A0 +1 110 sfr P2 = 0xA0; /* Port 2 */
00A8 +1 111 sfr IE = 0xA8; /* Interrupt Enable Register 0 */
00AA +1 112 sfr SPSR = 0xAA; /* SPI Status Register , different to AT89C52 */
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00B0 +1 114 sfr P3 = 0xB0; /* Port 3 */
00B8 +1 115 sfr IP = 0xB8; /* Interrupt Priority Register */
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00C8 +1 117 sfr T2CON = 0xC8; /* Timer 2 Control */
00C9 +1 118 sfr T2MOD = 0xC9; /* Timer 2 Mode */
00CA +1 119 sfr RCAP2L = 0xCA; /* Timer 2 Capture Low Byte */
00CB +1 120 sfr RCAP2H = 0xCB; /* Timer 2 Capture High Byte */
00CC +1 121 sfr TL2 = 0xCC; /* Timer 2 Low Byte */
00CD +1 122 sfr TH2 = 0xCD; /* Timer 2 High Byte */
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A51 MACRO ASSEMBLER STARTUP 11/26/2004 11:32:42 PAGE 3
00D0 +1 124 sfr PSW = 0xD0; /* Program Status Word */
00D5 +1 125 sfr SPCR = 0xD5; /* SPI Control Register , different to AT89C52 */
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00E0 +1 127 sfr ACC = 0xE0; /* Accumulator */
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00F0 +1 129 sfr B = 0xF0; /* B Register */
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0080 +1 134 sbit P0_0 = 0x80;
0081 +1 135 sbit P0_1 = 0x81;
0082 +1 136 sbit P0_2 = 0x82;
0083 +1 137 sbit P0_3 = 0x83;
0084 +1 138 sbit P0_4 = 0x84;
0085 +1 139 sbit P0_5 = 0x85;
0086 +1 140 sbit P0_6 = 0x86;
0087 +1 141 sbit P0_7 = 0x87;
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0088 +1 158 sbit IT0 = 0x88; /* Interrupt 0 Type Control Bit */
0089 +1 159 sbit IE0 = 0x89; /* Interrupt 0 Edge Flag */
008A +1 160 sbit IT1 = 0x8A; /* Interrupt 1 Type Control Bit */
008B +1 161 sbit IE1 = 0x8B; /* Interrupt 1 Edge Flag */
008C +1 162 sbit TR0 = 0x8C; /* Timer 0 Run Control Bit */
008D +1 163 sbit TF0 = 0x8D; /* Timer 0 Overflow Flag */
008E +1 164 sbit TR1 = 0x8E; /* Timer 1 Run Control Bit */
008F +1 165 sbit TF1 = 0x8F; /* Timer 1 Overflow Flag */
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0090 +1 186 sbit P1_0 = 0x90;
0091 +1 187 sbit P1_1 = 0x91;
0092 +1 188 sbit P1_2 = 0x92;
0093 +1 189 sbit P1_3 = 0x93;
A51 MACRO ASSEMBLER STARTUP 11/26/2004 11:32:42 PAGE 4
0094 +1 190 sbit P1_4 = 0x94;
0095 +1 191 sbit P1_5 = 0x95;
0096 +1 192 sbit P1_6 = 0x96;
0097 +1 193 sbit P1_7 = 0x97;
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0090 +1 195 sbit T2 = 0x90; /* External input to Timer/Counter 2, clock out */
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