📄 nicwinreg.h
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/*******************************************************************************
*** Note: Copy rights resevered to Beijing Pacific Linkair Communications Co.
***
*** File Name: NICWinReg.h
*** Purpose : NIC Window 0-7 Registers Definitions
***
*** Author : Guangzhao Tian
*** Modified : By Guangzhao Tian at 2000/9/7
***
**/
/* Window definitions.*/
#define REGISTER_WINDOW_0 0x0 /* setup/configuration */
#define REGISTER_WINDOW_1 0x1 /*/ operating set */
#define REGISTER_WINDOW_2 0x2 /* station address setup/read */
#define REGISTER_WINDOW_3 0x3 /* FIFO management */
#define REGISTER_WINDOW_4 0x4 /* diagnostics */
#define REGISTER_WINDOW_5 0x5 /* registers set by commands */
#define REGISTER_WINDOW_6 0x6 /* statistics */
#define REGISTER_WINDOW_7 0x7 /* bus master control*/
#define REGISTER_WINDOW_MASK 0xE000
/*-------- Register definitions ----------*/
#define INTSTATUS_INTERRUPT_MASK 0x6EE
/***** Window 0 registers. *******/
#define BIOS_ROM_ADDRESS_REGISTER 0x4
#define BIOS_ROM_DATA_REGISTER 0x8
#define EEPROM_COMMAND_REGISTER 0xA
#define EEPROM_BUSY_BIT BIT_15
#define EEPROM_COMMAND_READ 0x0080
#define EEPROM_WRITE_ENABLE 0x0030
#define EEPROM_ERASE_REGISTER 0x00C0
#define EEPROM_WRITE_REGISTER 0x0040
#define EEPROM_DATA_REGISTER 0xC
#define INTSTATUS_COMMAND_REGISTER 0xE
#define INTSTATUS_INTERRUPT_LATCH BIT_0
#define INTSTATUS_HOST_ERROR BIT_1
#define INTSTATUS_TX_COMPLETE BIT_2
#define INTSTATUS_RX_COMPLETE BIT_4
#define INTSTATUS_INTERRUPT_REQUESTED BIT_6
#define INTSTATUS_UPDATE_STATISTICS BIT_7
#define INTSTATUS_LINK_EVENT BIT_8
#define INTSTATUS_DOWN_COMPLETE BIT_9
#define INTSTATUS_UP_COMPLETE BIT_10
#define INTSTATUS_COMMAND_IN_PROGRESS BIT_12
#define INTSTATUS_INTERRUPT_NONE 0
#define INTSTATUS_INTERRUPT_ALL 0x6EE
#define INTSTATUS_ACKNOWLEDGE_ALL 0x7FF
/* Window 2 registers. */
#define STATION_ADDRESS_LOW_REGISTER 0x0
#define STATION_ADDRESS_MID_REGISTER 0x2
#define STATION_ADDRESS_HIGH_REGISTER 0x4
/* Window 3 registers. */
#define INTERNAL_CONFIG_REGISTER 0x0
#define INTERNAL_CONFIG_DISABLE_BAD_SSD BIT_8
#define INTERNAL_CONFIG_ENABLE_TX_LARGE BIT_14
#define INTERNAL_CONFIG_ENABLE_RX_LARGE BIT_15
#define INTERNAL_CONFIG_AUTO_SELECT BIT_24
#define INTERNAL_CONFIG_DISABLE_ROM BIT_25
#define INTERNAL_CONFIG_TRANSCEIVER_MASK 0x00F00000L
#define MAXIMUM_PACKET_SIZE_REGISTER 0x4
#define MAC_CONTROL_REGISTER 0x6
#define MAC_CONTROL_FULL_DUPLEX_ENABLE BIT_5
#define MAC_CONTROL_ALLOW_LARGE_PACKETS BIT_6
#define MAC_CONTROL_FLOW_CONTROL_ENABLE BIT_8
#define MEDIA_OPTIONS_REGISTER 0x8
#define MEDIA_OPTIONS_100BASET4_AVAILABLE BIT_0
#define MEDIA_OPTIONS_100BASETX_AVAILABLE BIT_1
#define MEDIA_OPTIONS_100BASEFX_AVAILABLE BIT_2
#define MEDIA_OPTIONS_10BASET_AVAILABLE BIT_3
#define MEDIA_OPTIONS_10BASE2_AVAILABLE BIT_4
#define MEDIA_OPTIONS_10AUI_AVAILABLE BIT_5
#define MEDIA_OPTIONS_MII_AVAILABLE BIT_6
#define MEDIA_OPTIONS_10BASEFL_AVAILABLE BIT_8
#define RX_FREE_REGISTER 0xA
#define TX_FREE_REGISTER 0xC
/* Window 4 registers.*/
#define PHYSICAL_MANAGEMENT_REGISTER 0x8
#define NETWORK_DIAGNOSTICS_REGISTER 0x6
#define NETWORK_DIAGNOSTICS_ASIC_REVISION 0x003E
#define NETWORK_DIAGNOSTICS_ASIC_REVISION_LOW 0x000E
#define NETWORK_DIAGNOSTICS_UPPER_BYTES_ENABLE BIT_6
#define MEDIA_STATUS_REGISTER 0xA
#define MEDIA_STATUS_SQE_STATISTICS_ENABLE BIT_3
#define MEDIA_STATUS_CARRIER_SENSE BIT_5
#define MEDIA_STATUS_JABBER_GUARD_ENABLE BIT_6
#define MEDIA_STATUS_LINK_BEAT_ENABLE BIT_7
#define MEDIA_STATUS_LINK_DETECT BIT_11
#define MEDIA_STATUS_TX_IN_PROGRESS BIT_12
#define MEDIA_STATUS_DC_CONVERTER_ENABLED BIT_14
#define BAD_SSD_REGISTER 0xC
#define UPPER_BYTES_OK_REGISTER 0xD
/* Window 5 registers. */
#define RX_FILTER_REGISTER 0x8
#define INTERRUPT_ENABLE_REGISTER 0xA
#define INDICATION_ENABLE_REGISTER 0xC
/* Window 6 registers.*/
#define CARRIER_LOST_REGISTER 0x0
#define SQE_ERRORS_REGISTER 0x1
#define MULTIPLE_COLLISIONS_REGISTER 0x2
#define SINGLE_COLLISIONS_REGISTER 0x3
#define LATE_COLLISIONS_REGISTER 0x4
#define RX_OVERRUNS_REGISTER 0x5
#define FRAMES_TRANSMITTED_OK_REGISTER 0x6
#define FRAMES_RECEIVED_OK_REGISTER 0x7
#define FRAMES_DEFERRED_REGISTER 0x8
#define UPPER_FRAMES_OK_REGISTER 0x9
#define BYTES_RECEIVED_OK_REGISTER 0xA
#define BYTES_TRANSMITTED_OK_REGISTER 0xC
/* Window 7 registers. */
#define VLAN_MASK 0x0
#define VLAN_ETHERNET_TYPE 0x4
#define POWER_MAGNEMENT_EVENT 0xc
/* Following are Window 7 Registers (Bus Master Control Version) */
#define BM_FRAGMENT_ADDRESS_WIN7 0x0
#define BM_FRAGMENT_LENGTH_WIN7 0x6
#define BUS_MASTER_STATUS_WIN7 0xB
#define BUS_MASTER_TIMER_WIN7 0xA
/***********************************************
**** Register Layout definition,
**** it's beyond 0x10, meaning not the window registers
***/
#define TX_PKTID 0x18
#define TIMER_REGISTER 0x1A
#define TX_STATUS_REGISTER 0x1B
#define TX_STATUS_RECLAIM_ERROR BIT_1
#define TX_STATUS_STACK_OVERFLOW BIT_2
#define TX_STATUS_MAXIMUM_COLLISION BIT_3
#define TX_STATUS_HWERROR BIT_4
#define TX_STATUS_JABBER BIT_5
#define TX_STATUS_INTERRUPT_REQUESTED BIT_6
#define TX_STATUS_COMPLETE BIT_7
#define INT_STATUS_AUTO_REGISTER 0x1E
#define DMA_CONTROL_REGISTER 0x20
#define DMA_CONTROL_DOWN_STALLED BIT_2
#define DMA_CONTROL_UP_COMPLETE BIT_3
#define DMA_CONTROL_DOWN_COMPLETE BIT_4
#define DMA_CONTROL_ARM_COUNTDOWN BIT_6
#define DMA_CONTROL_DOWN_IN_PROGRESS BIT_7
#define DMA_CONTROL_COUNTER_SPEED BIT_8
#define DMA_CONTROL_COUNTDOWN_MODE BIT_9
#define DMA_CONTROL_DOWN_SEQ_DISABLE BIT_17
#define DMA_CONTROL_DEFEAT_MWI BIT_20
#define DMA_CONTROL_DEFEAT_MRL BIT_21
#define DMA_CONTROL_UPOVERDISC_DISABLE BIT_22
#define DMA_CONTROL_TARGET_ABORT BIT_30
#define DMA_CONTROL_MASTER_ABORT BIT_31
#define DOWN_LIST_POINTER_REGISTER 0x24
#define BUS_MASTER_FRAGMENT_ADDRESS 0x28
#define BUS_MASTER_FRAGMENT_LENGTH 0x2C
#define DOWN_POLL_REGISTER 0x2D
#define BUS_MASTER_TXFREETHRESH 0x2F
#define UP_PACKET_STATUS_REGISTER 0x30
#define UP_PACKET_STATUS_ERROR BIT_14
#define UP_PACKET_STATUS_COMPLETE BIT_15
#define UP_PACKET_STATUS_OVERRUN BIT_16
#define UP_PACKET_STATUS_RUNT_FRAME BIT_17
#define UP_PACKET_STATUS_ALIGNMENT_ERROR BIT_18
#define UP_PACKET_STATUS_CRC_ERROR BIT_19
#define UP_PACKET_STATUS_OVERSIZE_FRAME BIT_20
#define UP_PACKET_STATUS_DRIBBLE_BITS BIT_23
#define UP_PACKET_STATUS_OVERFLOW BIT_24
#define UP_PACKET_STATUS_IP_CHECKSUM_ERROR BIT_25
#define UP_PACKET_STATUS_TCP_CHECKSUM_ERROR BIT_26
#define UP_PACKET_STATUS_UDP_CHECKSUM_ERROR BIT_27
#define UP_PACKET_STATUS_IMPLIED_BUFFER_ENABLE BIT_28
#define UP_PACKET_STATUS_IP_CHECKSUM_CHECKED BIT_29
#define UP_PACKET_STATUS_TCP_CHECKSUM_CHECKED BIT_30
#define UP_PACKET_STATUS_UDP_CHECKSUM_CHECKED BIT_31
#define UP_PACKET_LENGTH_MASK 0x1FFF
#define UP_PACKET_STATUS_ERROR_MASK 0x1F0000
#define FREE_TIMER_REGISTER 0x34
#define COUNTDOWN_REGISTER 0x36
#define UP_LIST_POINTER_REGISTER 0x38
#define UP_POLL_REGISTER 0x3D
#define REAL_TIME_COUNTER_REGISTER 0x40
#define CONFIG_ADDRESS_REGISTER 0x44
#define CONFIG_DATA_REGISTER 0x48
#define DEBUG_DATA_REGISTER 0x70
#define DEBUG_CONTROL_REGISTER 0x74
/** Macros of Windows Registers
*** end of WinRegisters.h
****************************************************************************************************/⌨️ 快捷键说明
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