nicmii.h

3com3c905网卡驱动程序

/*******************************************************************************
*** Note: Copy rights resevered to Beijing Pacific Linkair Communications Co. 
***
*** File Name: NICMii.h
*** Purpose  : Macros used by MII and Media Setting 
***
*** Author   : Guangzhao Tian
*** Modified : By Guangzhao Tian at 2000/9/12
***
**/
#define MII_WAITTIMES 			1
#define MII_RESETWAITTIMEs      400

/* Command line media override values */
#define MEDIA_NONE				0
#define MEDIA_10BASE_T			1
#define MEDIA_10AUI				2
#define MEDIA_10BASE_2			3
#define MEDIA_100BASE_TX		4
#define MEDIA_100BASE_FX		5
#define MEDIA_10BASE_FL			6
#define MEDIA_AUTO_SELECT		7

/* MII Management Address and Frame Format */
#define MII_PHY_ADDRESS				0x0C00
#define MII_PHY_READCOMMAND			MII_PHY_ADDRESS | 0x6000
#define MII_PHY_WRITECOMMAND        MII_PHY_ADDRESS | 0x5002

/*--------------------- MII register definitions -------------------- */
#define MII_PHY_CONTROL					0   /* control reg address */
#define MII_PHY_STATUS              	1   /* status reg address */
#define MII_PHY_OUI                 	2   /* most of the OUI bits */
#define MII_PHY_MODEL               	3   /* model/rev bits, and rest of OUI */
#define MII_PHY_ANAR                	4   /* Auto negotiate advertisement reg */
#define MII_PHY_ANLPAR              	5   /* auto negotiate Link Partner */
#define MII_PHY_ANER                	0x6
#define MII_PCR                     	0x17 /* PCS Config register */
#define MII_PAR                     	0x19

#define MII_PHY_REGISTER_24				24   /* Register 24 of the MII */
#define MII_PHY_REGISTER_24_PVCIRC		0x01 /* Process Variation Circuit bit */

/*--------------------- Bit definitions: Physical Management -------------------- */
#define PHY_WRITE			0x0004  /* Write to PHY (drive MDIO) */
#define PHY_DATA1			0x0002  /* MDIO data bit */
#define PHY_CLOCK			0x0001  /*/ MII clock signal */

/*--------------------- Bit definitions: MII Control --------------------*/
#define MII_CONTROL_RESET			0x8000  /* reset bit in control reg */
#define MII_CONTROL_100MB			0x2000  /* 100Mbit or 10 Mbit flag */
#define MII_CONTROL_ENABLE_AUTO		0x1000  /* autonegotiate enable */
#define MII_CONTROL_ISOLATE			0x0400  /* islolate bit */
#define MII_CONTROL_START_AUTO		0x0200  /* restart autonegotiate */
#define MII_CONTROL_FULL_DUPLEX		0x0100

/*--------------------- Bit definitions: MII Status -------------------- */
#define MII_STATUS_100MB_MASK	0xE000  /* any of these indicate 100 Mbit */
#define MII_STATUS_10MB_MASK	0x1800  /* either of these indicate 10 Mbit */
#define MII_STATUS_AUTO_DONE	0x0020  /* auto negotiation complete */
#define MII_STATUS_AUTO			0x0008  /* auto negotiation is available */
#define MII_STATUS_LINK_UP		0x0004  /* link status bit */
#define MII_STATUS_EXTENDED		0x0001  /* extended regs exist */
#define MII_STATUS_100T4		0x8000  /* capable of 100BT4 */
#define MII_STATUS_100TXFD		0x4000  /* capable of 100BTX full duplex */
#define MII_STATUS_100TX		0x2000  /* capable of 100BTX */
#define MII_STATUS_10TFD		0x1000  /* capable of 10BT full duplex */
#define MII_STATUS_10T			0x0800  /* capable of 10BT */

/*----------- Bit definitions: Auto-Negotiation Link Partner Ability ---------- */
#define MII_ANLPAR_100T4	0x0200  /* support 100BT4 */
#define MII_ANLPAR_100TXFD	0x0100  /* support 100BTX full duplex */
#define MII_ANLPAR_100TX	0x0080  /* support 100BTX half duplex */
#define MII_ANLPAR_10TFD	0x0040  /* support 10BT full duplex */
#define MII_ANLPAR_10T		0x0020  /* support 10BT half duplex*/

/*----------- Bit definitions: Auto-Negotiation Advertisement ----------*/
#define MII_ANAR_100T4			0x0200  /* support 100BT4 */
#define MII_ANAR_100TXFD		0x0100  /* support 100BTX full duplex */
#define MII_ANAR_100TX			0x0080  /* support 100BTX half duplex */
#define MII_ANAR_10TFD			0x0040  /* support 10BT full duplex */
#define MII_ANAR_10T			0x0020  /* support 10BT half duplex */
#define MII_ANAR_FLOWCONTROL	0x0400  /* support Flow Control*/

#define MII_ANAR_MEDIA_MASK		0x07E0	/* Mask the media selection bits*/
#define MII_ANAR_MEDIA_100_MASK	(MII_ANAR_100TXFD | MII_ANAR_100TX)
#define MII_ANAR_MEDIA_10_MASK	(MII_ANAR_10TFD | MII_ANAR_10T)

#define MII_100TXFD		0x01
#define MII_100T4		0x02
#define MII_100TX		0x03
#define MII_10TFD		0x04
#define MII_10T			0x05

/*----------- Bit definitions: Auto-Negotiation Expansion ---------- */
#define MII_ANER_LPANABLE	0x0001  /* Link partner autonegotiatable ? */
#define MII_ANER_MLF		0x0010  /* Multiple Link Fault bit */

/* MII Transceiver Type store in miiSelect*/
#define MIISELECT_GENERIC		0x0000
#define MIISELECT_100BT4		0x0001
#define MIISELECT_10BT			0x0002
#define MIISELECT_100BTX		0x0003
#define MIISELECT_10BT_ANE		0x0004
#define MIISELECT_100BTX_ANE	0x0005
#define MIITXTYPE_MASK			0x000F
									 

/**  Above are definitions of the MII module
***  End of NICMii.h
**********************************************************************************/