📄 e100bexhw.h
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BOOLEAN MWIEnable; // Memory Write Invalidate bit
UINT McTimeoutFlag; // MC workaround flag
UINT PhyAddress;
UCHAR Connector; // 0=Auto, 1=TPE, 2=MII
} ADAPTER_INFO, *PADAPTER_INFO;
//-------------------------------------------------------------------------
// Error Counters
//-------------------------------------------------------------------------
typedef struct _ERR_COUNT_STRUC {
ULONG XmtGoodFrames; // Good frames transmitted
ULONG XmtMaxCollisions; // Fatal frames -- had max collisions
ULONG XmtLateCollisions; // Fatal frames -- had a late coll.
ULONG XmtUnderruns; // Transmit underruns (fatal or re-transmit)
ULONG XmtLostCRS; // Frames transmitted without CRS
ULONG XmtDeferred; // Deferred transmits
ULONG XmtSingleCollision; // Transmits that had 1 and only 1 coll.
ULONG XmtMultCollisions; // Transmits that had multiple coll.
ULONG XmtTotalCollisions; // Transmits that had 1+ collisions.
ULONG RcvGoodFrames; // Good frames received
ULONG RcvCrcErrors; // Aligned frames that had a CRC error
ULONG RcvAlignmentErrors; // Receives that had alignment errors
ULONG RcvResourceErrors; // Good frame dropped due to lack of resources
ULONG RcvOverrunErrors; // Overrun errors - bus was busy
ULONG RcvCdtErrors; // Received frames that encountered coll.
ULONG RcvShortFrames; // Received frames that were to short
ULONG CommandComplete; // A005h indicates cmd completion
} ERR_COUNT_STRUC, *PERR_COUNT_STRUC;
//-------------------------------------------------------------------------
// Command Block (CB) Generic Header Structure
//-------------------------------------------------------------------------
typedef struct _CB_HEADER_STRUC {
USHORT CbStatus; // Command Block Status
USHORT CbCommand; // Command Block Command
ULONG CbLinkPointer; // Link To Next CB
} CB_HEADER_STRUC, *PCB_HEADER_STRUC;
//-------------------------------------------------------------------------
// NOP Command Block (NOP_CB)
//-------------------------------------------------------------------------
typedef struct _NOP_CB_STRUC {
CB_HEADER_STRUC NopCBHeader;
} NOP_CB_STRUC, *PNOP_CB_STRUC;
//-------------------------------------------------------------------------
// Individual Address Command Block (IA_CB)
//-------------------------------------------------------------------------
typedef struct _IA_CB_STRUC {
CB_HEADER_STRUC IaCBHeader;
UCHAR IaAddress[ETHERNET_ADDRESS_LENGTH];
} IA_CB_STRUC, *PIA_CB_STRUC;
//-------------------------------------------------------------------------
// Configure Command Block (CONFIG_CB)
//-------------------------------------------------------------------------
typedef struct _CONFIG_CB_STRUC {
CB_HEADER_STRUC ConfigCBHeader;
UCHAR ConfigBytes[CB_CFIG_BYTE_COUNT];
} CONFIG_CB_STRUC, *PCONFIG_CB_STRUC;
//-------------------------------------------------------------------------
// MultiCast Command Block (MULTICAST_CB)
//-------------------------------------------------------------------------
typedef struct _MULTICAST_CB_STRUC {
CB_HEADER_STRUC McCBHeader;
USHORT McCount; // Number of multicast addresses
UCHAR McAddress[(ETHERNET_ADDRESS_LENGTH * MAX_MULTICAST_ADDRESSES)];
} MULTICAST_CB_STRUC, *PMULTICAST_CB_STRUC;
//-------------------------------------------------------------------------
// Dump Command Block (DUMP_CB)
//-------------------------------------------------------------------------
typedef struct _DUMP_CB_STRUC {
CB_HEADER_STRUC DumpCBHeader;
ULONG DumpAreaAddress; // Dump Buffer Area Address
} DUMP_CB_STRUC, *PDUMP_CB_STRUC;
//-------------------------------------------------------------------------
// Dump Area structure definition
//-------------------------------------------------------------------------
typedef struct _DUMP_AREA_STRUC {
UCHAR DumpBuffer[DUMP_BUFFER_SIZE];
} DUMP_AREA_STRUC, *PDUMP_AREA_STRUC;
//-------------------------------------------------------------------------
// Diagnose Command Block (DIAGNOSE_CB)
//-------------------------------------------------------------------------
typedef struct _DIAGNOSE_CB_STRUC {
CB_HEADER_STRUC DiagCBHeader;
} DIAGNOSE_CB_STRUC, *PDIAGNOSE_CB_STRUC;
//-------------------------------------------------------------------------
// Transmit Command Block (TxCB)
//-------------------------------------------------------------------------
typedef struct _GENERIC_TxCB {
CB_HEADER_STRUC TxCbHeader;
ULONG TxCbTbdPointer; // TBD address
USHORT TxCbCount; // Data Bytes In TCB past header
UCHAR TxCbThreshold; // TX Threshold for FIFO Extender
UCHAR TxCbTbdNumber;
ETH_TX_BUFFER_STRUC TxCbData;
ULONG pad0;
ULONG pad1;
ULONG pad2;
ULONG pad3;
} TXCB_STRUC, *PTXCB_STRUC;
//-------------------------------------------------------------------------
// Transmit Buffer Descriptor (TBD)
//-------------------------------------------------------------------------
typedef struct _TBD_STRUC {
ULONG TbdBufferAddress; // Physical Transmit Buffer Address
unsigned TbdCount :14;
unsigned :1 ; // always 0
unsigned EndOfList:1 ; // EL bit in Tbd
unsigned :16; // field that is always 0's in a TBD
} TBD_STRUC, *PTBD_STRUC;
//-------------------------------------------------------------------------
// Receive Buffer Descriptor (RBD)
//-------------------------------------------------------------------------
typedef struct _RBD_STRUC {
USHORT RbdActualCount; // Number Of Bytes Received
USHORT RbdFiller;
ULONG RbdLinkAddress; // Link To Next RBD
ULONG RbdRcbAddress; // Receive Buffer Address
USHORT RbdSize; // Receive Buffer Size
USHORT RbdFiller1;
} RBD_STRUC, *PRBD_STRUC;
#pragma pack()
//-------------------------------------------------------------------------
// PHY 100 MDI Register/Bit Definitions
//-------------------------------------------------------------------------
// MDI register set
const UCHAR MDI_CONTROL_REG = 0x00; // MDI control register
const UCHAR MDI_STATUS_REG = 0x01; // MDI Status regiser
const UCHAR PHY_ID_REG_1 = 0x02; // Phy indentification reg (word 1)
const UCHAR PHY_ID_REG_2 = 0x03; // Phy indentification reg (word 2)
const UCHAR AUTO_NEG_ADVERTISE_REG = 0x04; // Auto-negotiation advertisement
const UCHAR AUTO_NEG_LINK_PARTNER_REG = 0x05; // Auto-negotiation link partner ability
const UCHAR AUTO_NEG_EXPANSION_REG = 0x06; // Auto-negotiation expansion
const UCHAR AUTO_NEG_NEXT_PAGE_REG = 0x07; // Auto-negotiation next page transmit
const UCHAR EXTENDED_REG_0 = 0x10; // Extended reg 0 (Phy 100 modes)
const UCHAR EXTENDED_REG_1 = 0x14; // Extended reg 1 (Phy 100 error indications)
const UCHAR NSC_CONG_CONTROL_REG = 0x17; // National (TX) congestion control
const UCHAR NSC_SPEED_IND_REG = 0x19; // National (TX) speed indication
const UCHAR PHY_EQUALIZER_REG = 0x1A; // Register for the Phy Equalizer values
// MDI Control register bit definitions
const USHORT MDI_CR_COLL_TEST_ENABLE = BIT_7; // Collision test enable
const USHORT MDI_CR_FULL_HALF = BIT_8; // FDX =1, half duplex =0
const USHORT MDI_CR_RESTART_AUTO_NEG = BIT_9; // Restart auto negotiation
const USHORT MDI_CR_ISOLATE = BIT_10; // Isolate PHY from MII
const USHORT MDI_CR_POWER_DOWN = BIT_11; // Power down
const USHORT MDI_CR_AUTO_SELECT = BIT_12; // Auto speed select enable
const USHORT MDI_CR_10_100 = BIT_13; // 0 = 10Mbs, 1 = 100Mbs
const USHORT MDI_CR_LOOPBACK = BIT_14; // 0 = normal, 1 = loopback
const USHORT MDI_CR_RESET = BIT_15; // 0 = normal, 1 = PHY reset
// MDI Status register bit definitions
const USHORT MDI_SR_EXT_REG_CAPABLE = BIT_0; // Extended register capabilities
const USHORT MDI_SR_JABBER_DETECT = BIT_1; // Jabber detected
const USHORT MDI_SR_LINK_STATUS = BIT_2; // Link Status -- 1 = link
const USHORT MDI_SR_AUTO_SELECT_CAPABLE = BIT_3; // Auto speed select capable
const USHORT MDI_SR_REMOTE_FAULT_DETECT = BIT_4; // Remote fault detect
const USHORT MDI_SR_AUTO_NEG_COMPLETE = BIT_5; // Auto negotiation complete
const USHORT MDI_SR_10T_HALF_DPX = BIT_11; // 10BaseT Half Duplex capable
const USHORT MDI_SR_10T_FULL_DPX = BIT_12; // 10BaseT full duplex capable
const USHORT MDI_SR_TX_HALF_DPX = BIT_13; // TX Half Duplex capable
const USHORT MDI_SR_TX_FULL_DPX = BIT_14; // TX full duplex capable
const USHORT MDI_SR_T4_CAPABLE = BIT_15; // T4 capable
// Auto-Negotiation advertisement register bit definitions
const USHORT NWAY_AD_SELCTOR_FIELD = BIT_0_4; // identifies supported protocol
const USHORT NWAY_AD_ABILITY = BIT_5_12; // technologies that are supported
const USHORT NWAY_AD_10T_HALF_DPX = BIT_5; // 10BaseT Half Duplex capable
const USHORT NWAY_AD_10T_FULL_DPX = BIT_6; // 10BaseT full duplex capable
const USHORT NWAY_AD_TX_HALF_DPX = BIT_7; // TX Half Duplex capable
const USHORT NWAY_AD_TX_FULL_DPX = BIT_8; // TX full duplex capable
const USHORT NWAY_AD_T4_CAPABLE = BIT_9; // T4 capable
const USHORT NWAY_AD_REMOTE_FAULT = BIT_13; // indicates local remote fault
const USHORT NWAY_AD_RESERVED = BIT_14; // reserved
const USHORT NWAY_AD_NEXT_PAGE = BIT_15; // Next page (not supported)
// Auto-Negotiation link partner ability register bit definitions
const USHORT NWAY_LP_SELCTOR_FIELD = BIT_0_4; // identifies supported protocol
const USHORT NWAY_LP_ABILITY = BIT_5_9; // technologies that are supported
const USHORT NWAY_LP_REMOTE_FAULT = BIT_13; // indicates partner remote fault
const USHORT NWAY_LP_ACKNOWLEDGE = BIT_14; // acknowledge
const USHORT NWAY_LP_NEXT_PAGE = BIT_15; // Next page (not supported)
// Auto-Negotiation expansion register bit definitions
const USHORT NWAY_EX_LP_NWAY = BIT_0; // link partner is NWAY
const USHORT NWAY_EX_PAGE_RECEIVED = BIT_1; // link code word received
const USHORT NWAY_EX_NEXT_PAGE_ABLE = BIT_2; // local is next page able
const USHORT NWAY_EX_LP_NEXT_PAGE_ABLE = BIT_3; // partner is next page able
const USHORT NWAY_EX_PARALLEL_DET_FLT = BIT_4; // parallel detection fault
const USHORT NWAY_EX_RESERVED = BIT_5_15; // reserved
// PHY 100 Extended Register 0 bit definitions
const USHORT PHY_100_ER0_FDX_INDIC = BIT_0; // 1 = FDX, 0 = half duplex
const USHORT PHY_100_ER0_SPEED_INDIC = BIT_1; // 1 = 100mbs, 0= 10mbs
const USHORT PHY_100_ER0_WAKE_UP = BIT_2; // Wake up DAC
const USHORT PHY_100_ER0_RESERVED = BIT_3_4; // Reserved
const USHORT PHY_100_ER0_REV_CNTRL = BIT_5_7; // Revsion control (A step = 000)
const USHORT PHY_100_ER0_FORCE_FAIL = BIT_8; // Force Fail is enabled
const USHORT PHY_100_ER0_TEST = BIT_9_13; // Revsion control (A step = 000)
const USHORT PHY_100_ER0_LINKDIS = BIT_14; // Link integrity test is disabled
const USHORT PHY_100_ER0_JABDIS = BIT_15; // Jabber function is disabled
// PHY 100 Extended Register 1 bit definitions
const USHORT PHY_100_ER1_RESERVED = BIT_0_8; // Reserved
const USHORT PHY_100_ER1_CH2_DET_ERR = BIT_9; // Channel 2 EOF detection error
const USHORT PHY_100_ER1_MANCH_CODE_ERR = BIT_10; // Manchester code error
const USHORT PHY_100_ER1_EOP_ERR = BIT_11; // EOP error
const USHORT PHY_100_ER1_BAD_CODE_ERR = BIT_12; // bad code error
const USHORT PHY_100_ER1_INV_CODE_ERR = BIT_13; // invalid code error
const USHORT PHY_100_ER1_DC_BAL_ERR = BIT_14; // DC balance error
const USHORT PHY_100_ER1_PAIR_SKEW_ERR = BIT_15; // Pair skew error
// PHY TX Register/Bit definitions
const UCHAR PHY_TX_STATUS_CTRL_REG = 0x10;
const USHORT PHY_TX_POLARITY_MASK = BIT_8; // register 10h bit 8 (the polarity bit)
const UCHAR PHY_TX_NORMAL_POLARITY = 0; // register 10h bit 8 =0 (normal polarity)
const UCHAR PHY_TX_SPECIAL_CTRL_REG = 0x11;
const USHORT AUTO_POLARITY_DISABLE = BIT_4; // register 11h bit 4 (0=enable, 1=disable)
const UCHAR PHY_TX_REG_18 = 0x18; // Error counter register
// National Semiconductor TX phy congestion control register bit definitions
const USHORT NSC_TX_CONG_TXREADY = BIT_10; // Makes TxReady an input
const USHORT NSC_TX_CONG_ENABLE = BIT_8; // Enables congestion control
const USHORT NSC_TX_CONG_F_CONNECT = BIT_5; // Enables congestion control
// National Semiconductor TX phy speed indication register bit definitions
const USHORT NSC_TX_SPD_INDC_SPEED = BIT_6; // 0 = 100mb, 1=10mb
//-------------------------------------------------------------------------
// MDI Control register bit definitions
//-------------------------------------------------------------------------
const USHORT MDI_DATA_MASK = BIT_0_15; // MDI Data port
const ULONG MDI_REG_ADDR = BIT_16_20; // which MDI register to read/write
const ULONG MDI_PHY_ADDR = BIT_21_25; // which PHY to read/write
const ULONG MDI_PHY_OPCODE = BIT_26_27; // which PHY to read/write
const ULONG MDI_PHY_READY = BIT_28; // PHY is ready for another MDI cycle
const ULONG MDI_PHY_INT_ENABLE = BIT_29; // Assert INT at MDI cycle completion
//-------------------------------------------------------------------------
// MDI Control register opcode definitions
//-------------------------------------------------------------------------
const UCHAR MDI_WRITE = 1; // Phy Write
const UCHAR MDI_READ = 2; // Phy read
//-------------------------------------------------------------------------
// Phy related constants
//-------------------------------------------------------------------------
const UCHAR PHY_503 = 0;
const ULONG PHY_100_A = 0x000003E0;
const ULONG PHY_100_C = 0x035002A8;
const ULONG PHY_TX_ID = 0x015002A8;
const ULONG PHY_NSC_TX = 0x5c002000;
const USHORT PHY_OTHER = 0xFFFF;
const ULONG PHY_MODEL_REV_ID_MASK = 0xFFF0FFFF;
const UCHAR PARALLEL_DETECT = 0;
const UCHAR N_WAY = 1;
const UCHAR RENEGOTIATE_TIME = 35; // (3.5 Seconds)
const UCHAR CONNECTOR_AUTO = 0;
const UCHAR CONNECTOR_TPE = 1;
const UCHAR CONNECTOR_MII = 2;
#endif // !defined(AFX_E100BEXHW_H__0E5098AF_1538_11D4_AFF3_00C04F6A5DA9__INCLUDED_)
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