📄 e100bexhw.h
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const USHORT CB_CFIG_RX_MIN_DMA_MASK = BIT_0_6; // Rx minimum DMA count mask
// byte 5 bit definitions
const USHORT CB_CFIG_TX_MIN_DMA_MASK = BIT_0_6; // Tx minimum DMA count mask
const USHORT CB_CFIG_DMBC_EN = BIT_7; // Enable Tx/Rx minimum DMA counts
// byte 6 bit definitions
const USHORT CB_CFIG_LATE_SCB = BIT_0; // Update SCB After New Tx Start
const USHORT CB_CFIG_TNO_INT = BIT_2; // Tx Not OK Interrupt
const USHORT CB_CFIG_CI_INT = BIT_3; // Command Complete Interrupt
const USHORT CB_CFIG_SAVE_BAD_FRAMES = BIT_7; // Save Bad Frames Enabled
// byte 7 bit definitions
const USHORT CB_CFIG_DISC_SHORT_FRAMES = BIT_0; // Discard Short Frames
const USHORT CB_CFIG_URUN_RETRY = BIT_1_2; // Underrun Retry Count
// byte 8 bit definitions
const USHORT CB_CFIG_503_MII = BIT_0; // 503 vs. MII mode
// byte 9 bit definitions -- pre-defined all zeros
// byte 10 bit definitions
const USHORT CB_CFIG_NO_SRCADR = BIT_3; // No Source Address Insertion
const USHORT CB_CFIG_PREAMBLE_LEN = BIT_4_5; // Preamble Length
const USHORT CB_CFIG_LOOPBACK_MODE = BIT_6_7; // Loopback Mode
// byte 11 bit definitions
const USHORT CB_CFIG_LINEAR_PRIORITY = BIT_0_2; // Linear Priority
// byte 12 bit definitions
const USHORT CB_CFIG_LINEAR_PRI_MODE = BIT_0; // Linear Priority mode
const USHORT CB_CFIG_IFS_MASK = BIT_4_7; // CSMA level Interframe Spacing mask
// byte 13 bit definitions -- pre-defined all zeros
// byte 14 bit definitions -- pre-defined 0xf2
// byte 15 bit definitions
const USHORT CB_CFIG_PROMISCUOUS = BIT_0; // Promiscuous Mode Enable
const USHORT CB_CFIG_BROADCAST_DIS = BIT_1; // Broadcast Mode Disable
const USHORT CB_CFIG_CRS_OR_CDT = BIT_7; // CRS Or CDT
// byte 16 bit definitions -- pre-defined all zeros
// byte 17 bit definitions -- pre-defined 0x40
// byte 18 bit definitions
const USHORT CB_CFIG_STRIPPING = BIT_0; // Stripping Disabled
const USHORT CB_CFIG_PADDING = BIT_1; // Padding Disabled
const USHORT CB_CFIG_CRC_IN_MEM = BIT_2; // Transfer CRC To Memory
// byte 19 bit definitions
const USHORT CB_CFIG_FORCE_FDX = BIT_6; // Force Full Duplex
const USHORT CB_CFIG_FDX_ENABLE = BIT_7; // Full Duplex Enabled
// byte 20 bit definitions
const USHORT CB_CFIG_MULTI_IA = BIT_6; // Multiple IA Addr
// byte 21 bit definitions
const USHORT CB_CFIG_MULTICAST_ALL = BIT_3; // Multicast All
//-------------------------------------------------------------------------
// Receive Frame Descriptor Fields
//-------------------------------------------------------------------------
//- RFD Status Bits
const USHORT RFD_RECEIVE_COLLISION = BIT_0; // Collision detected on Receive
const USHORT RFD_IA_MATCH = BIT_1; // Indv Address Match Bit
const USHORT RFD_RX_ERR = BIT_4; // RX_ERR pin on Phy was set
const USHORT RFD_FRAME_TOO_SHORT = BIT_7; // Receive Frame Short
const USHORT RFD_DMA_OVERRUN = BIT_8; // Receive DMA Overrun
const USHORT RFD_NO_RESOURCES = BIT_9; // No Buffer Space
const USHORT RFD_ALIGNMENT_ERROR = BIT_10; // Alignment Error
const USHORT RFD_CRC_ERROR = BIT_11; // CRC Error
const USHORT RFD_STATUS_OK = BIT_13; // RFD OK Bit
const USHORT RFD_STATUS_COMPLETE = BIT_15; // RFD Complete Bit
//- RFD Command Bits
const USHORT RFD_EL_BIT = BIT_15; // RFD EL Bit
const USHORT RFD_S_BIT = BIT_14; // RFD Suspend Bit
const USHORT RFD_H_BIT = BIT_4; // Header RFD Bit
const USHORT RFD_SF_BIT = BIT_3; // RFD Flexible Mode
//- RFD misc bits
const USHORT RFD_EOF_BIT = BIT_15; // RFD End-Of-Frame Bit
const USHORT RFD_F_BIT = BIT_14; // RFD Buffer Fetch Bit
const USHORT RFD_ACT_COUNT_MASK = BIT_0_13; // RFD Actual Count Mask
const USHORT RFD_HEADER_SIZE = 0x10; // Size of RFD Header (16 bytes)
//-------------------------------------------------------------------------
// Receive Buffer Descriptor Fields
//-------------------------------------------------------------------------
const USHORT RBD_EOF_BIT = BIT_15; // RBD End-Of-Frame Bit
const USHORT RBD_F_BIT = BIT_14; // RBD Buffer Fetch Bit
const USHORT RBD_ACT_COUNT_MASK = BIT_0_13; // RBD Actual Count Mask
const USHORT SIZE_FIELD_MASK = BIT_0_13; // Size of the associated buffer
const USHORT RBD_EL_BIT = BIT_15; // RBD EL Bit
//-------------------------------------------------------------------------
// Size Of Dump Buffer
//-------------------------------------------------------------------------
const USHORT DUMP_BUFFER_SIZE = 600; // size of the dump buffer
//-------------------------------------------------------------------------
// Self Test Results
//-------------------------------------------------------------------------
const USHORT CB_SELFTEST_FAIL_BIT = BIT_12;
const USHORT CB_SELFTEST_DIAG_BIT = BIT_5;
const USHORT CB_SELFTEST_REGISTER_BIT = BIT_3;
const USHORT CB_SELFTEST_ROM_BIT = BIT_2;
const USHORT CB_SELFTEST_ERROR_MASK = CB_SELFTEST_FAIL_BIT |
CB_SELFTEST_DIAG_BIT |
CB_SELFTEST_REGISTER_BIT |
CB_SELFTEST_ROM_BIT;
//-------------------------------------------------------------------------
// Driver Configuration Default Parameters for the 557
// Note: If the driver uses any defaults that are different from the chip's
// defaults, it will be noted below
//-------------------------------------------------------------------------
const USHORT CB_557_CFIG_DEFAULT_PARM0 = CB_CFIG_BYTE_COUNT; // Byte 0 (byte count) default
const UCHAR DEFAULT_TX_FIFO_LIMIT = 0x08; // Byte 1 (fifo limits) default
const UCHAR DEFAULT_RX_FIFO_LIMIT = 0x08;
const UCHAR CB_557_CFIG_DEFAULT_PARM1 = 0x88;
const UCHAR CB_557_CFIG_DEFAULT_PARM2 = 0x00; // Byte 2 (IFS) default
const UCHAR CB_557_CFIG_DEFAULT_PARM3 = 0x00; // Byte 3 (reserved) default
const UCHAR CB_557_CFIG_DEFAULT_PARM4 = 0x00; // Byte 4 (Rx DMA min count) default
const UCHAR CB_557_CFIG_DEFAULT_PARM5 = 0x00; // Byte 5 (Tx DMA min count, DMA min count enable) default
const UCHAR CB_557_CFIG_DEFAULT_PARM6 = 0x32; // Byte 6 (Late SCB, TNO int, CI int, Save bad frames) default
const UCHAR DEFAULT_UNDERRUN_RETRY = 0x01; // Byte 7 (Discard short frames, underrun retry) default
// note: disc short frames will be enabled
const UCHAR CB_557_CFIG_DEFAULT_PARM7 = 0x03;
const UCHAR CB_557_CFIG_DEFAULT_PARM8 = 0x01; // Byte 8 (MII or 503) default
// note: MII will be the default
const UCHAR CB_557_CFIG_DEFAULT_PARM9 = 0x00; // Byte 9 (reserved) default
const UCHAR CB_557_CFIG_DEFAULT_PARM10 = 0x2e; // Byte 10 (scr addr insertion, preamble, loopback) default
const UCHAR CB_557_CFIG_DEFAULT_PARM11 = 0x00; // Byte 11 (linear priority) default
const UCHAR CB_557_CFIG_DEFAULT_PARM12 = 0x60; // Byte 12 (IFS,linear priority mode) default
const UCHAR CB_557_CFIG_DEFAULT_PARM13 = 0x00; // Byte 13 (reserved) default
const UCHAR CB_557_CFIG_DEFAULT_PARM14 = 0xf2; // Byte 14 (reserved) default
const UCHAR CB_557_CFIG_DEFAULT_PARM15 = 0xc8; // Byte 15 (promiscuous, broadcast, CRS/CDT) default
const UCHAR CB_557_CFIG_DEFAULT_PARM16 = 0x00; // Byte 16 (reserved) default
const UCHAR CB_557_CFIG_DEFAULT_PARM17 = 0x40; // Byte 17 (reserved) default
const UCHAR CB_557_CFIG_DEFAULT_PARM18 = 0xf2; // Byte 18 (Stripping, padding, Rcv CRC in mem) default
// note: padding will be enabled
const UCHAR CB_557_CFIG_DEFAULT_PARM19 = 0x80; // Byte 19 (reserved) default
// note: full duplex is enabled if FDX# pin is 0
const UCHAR CB_557_CFIG_DEFAULT_PARM20 = 0x3f; // Byte 20 (multi-IA) default
const UCHAR CB_557_CFIG_DEFAULT_PARM21 = 0x05; // Byte 21 (multicast all) default
#pragma pack(1)
//-------------------------------------------------------------------------
// Ethernet Frame Structure
//-------------------------------------------------------------------------
//- Ethernet 6-byte Address
typedef struct _ETH_ADDRESS_STRUC {
UCHAR EthNodeAddress[ETHERNET_ADDRESS_LENGTH];
} ETH_ADDRESS_STRUC, *PETH_ADDRESS_STRUC;
//- Ethernet 14-byte Header
typedef struct _ETH_HEADER_STRUC {
UCHAR Destination[ETHERNET_ADDRESS_LENGTH];
UCHAR Source[ETHERNET_ADDRESS_LENGTH];
USHORT TypeLength;
} ETH_HEADER_STRUC, *PETH_HEADER_STRUC;
//- Ethernet Buffer (Including Ethernet Header) for Transmits
typedef struct _ETH_TX_BUFFER_STRUC {
ETH_HEADER_STRUC TxMacHeader;
UCHAR TxBufferData[(TCB_BUFFER_SIZE - sizeof(ETH_HEADER_STRUC))];
} ETH_TX_BUFFER_STRUC, *PETH_TX_BUFFER_STRUC;
typedef struct _ETH_RX_BUFFER_STRUC {
ETH_HEADER_STRUC RxMacHeader;
UCHAR RxBufferData[(RCB_BUFFER_SIZE - sizeof(ETH_HEADER_STRUC))];
} ETH_RX_BUFFER_STRUC, *PETH_RX_BUFFER_STRUC;
//-------------------------------------------------------------------------
// 82557 Data Structures
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Self test
//-------------------------------------------------------------------------
typedef struct _SELF_TEST_STRUC {
ULONG StSignature; // Self Test Signature
ULONG StResults; // Self Test Results
} SELF_TEST_STRUC, *PSELF_TEST_STRUC;
//-------------------------------------------------------------------------
// Control/Status Registers (CSR)
//-------------------------------------------------------------------------
typedef struct _CSR_STRUC {
USHORT ScbStatus; // SCB Status register/
UCHAR ScbCommandLow; // SCB Command register (low byte)
UCHAR ScbCommandHigh; // SCB Command register (high byte)
ULONG ScbGeneralPointer; // SCB General pointer
ULONG Port; // PORT register
USHORT FlashControl; // Flash Control register
USHORT EepromControl; // EEPROM control register
ULONG MDIControl; // MDI Control Register
ULONG RxDMAByteCount; // Receive DMA Byte count register
} CSR_STRUC, *PCSR_STRUC;
#define CSR_REG_OFFSET(field) (FIELD_OFFSET(CSR_STRUC,field))
struct CSRStruc
{
CSRStruc(KNdisMemoryRange &Range);
#if _MSC_VER > 1200
//The new Whistler cl.exe has not been able to compile KNdisMemoryRegisterSafe
// without crashing. This avoids the bug.
KNdisMemoryRegister ScbStatus; // SCB Status register
KNdisMemoryRegister ScbCommandLow; // SCB Command register (low byte)
KNdisMemoryRegister ScbCommandHigh; // SCB Command register (high byte)
KNdisMemoryRegister ScbGeneralPointer; // SCB General pointer
KNdisMemoryRegister Port; // PORT register
KNdisMemoryRegister FlashControl; // Flash Control register
KNdisMemoryRegister EepromControl; // EEPROM control register
KNdisMemoryRegister MDIControl; // MDI Control Register
KNdisMemoryRegister RxDMAByteCount; // Receive DMA Byte count register
#else
KNdisMemoryRegisterSafe<USHORT> ScbStatus; // SCB Status register
KNdisMemoryRegisterSafe<UCHAR> ScbCommandLow; // SCB Command register (low byte)
KNdisMemoryRegisterSafe<UCHAR> ScbCommandHigh; // SCB Command register (high byte)
KNdisMemoryRegisterSafe<ULONG> ScbGeneralPointer; // SCB General pointer
KNdisMemoryRegisterSafe<ULONG> Port; // PORT register
KNdisMemoryRegisterSafe<USHORT> FlashControl; // Flash Control register
KNdisMemoryRegisterSafe<USHORT> EepromControl; // EEPROM control register
KNdisMemoryRegisterSafe<ULONG> MDIControl; // MDI Control Register
KNdisMemoryRegisterSafe<ULONG> RxDMAByteCount; // Receive DMA Byte count register
#endif
};
typedef CSRStruc *PCSRStruc;
inline CSRStruc::CSRStruc(KNdisMemoryRange &Range)
{
ScbStatus = Range[CSR_REG_OFFSET(ScbStatus)];
ScbCommandLow = Range[CSR_REG_OFFSET(ScbCommandLow)];
ScbCommandHigh = Range[CSR_REG_OFFSET(ScbCommandHigh)];
ScbGeneralPointer = Range[CSR_REG_OFFSET(ScbGeneralPointer)];
Port = Range[CSR_REG_OFFSET(Port)];
FlashControl = Range[CSR_REG_OFFSET(FlashControl)];
EepromControl = Range[CSR_REG_OFFSET(EepromControl)];
MDIControl = Range[CSR_REG_OFFSET(MDIControl)];
RxDMAByteCount = Range[CSR_REG_OFFSET(RxDMAByteCount)];
}
typedef struct _ADAPTER_INFO {
USHORT AiTxFifo; // TX FIFO Threshold
USHORT AiRxFifo; // RX FIFO Threshold
USHORT AiTempSpeed; // 'Speed', user over-ride of line speed
UCHAR AiUnderrunRetry; // The underrun retry mechanism
UCHAR AiForceDpx; // duplex setting
UCHAR AiTxDmaCount; // Tx dma count
UCHAR AiRxDmaCount; // Rx dma count
UCHAR Congest; // Enables congestion control
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