📄 e100bexhw.h
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// E100bexHw.h: - Data structures and symbolic constants for the hardware.
//
//=============================================================================
//
// Compuware Corporation
// NuMega Lab
// 9 Townsend West
// Nashua, NH 03060 USA
//
// Copyright (c) 2000 Compuware Corporation. All Rights Reserved.
// Unpublished - rights reserved under the Copyright laws of the
// United States.
//
//=============================================================================
//
// Portions copied from Microsoft Windows 2000 DDK sample driver containing the
// following copyright
//
/****************************************************************************
** COPYRIGHT (C) 1994-1997 INTEL CORPORATION **
** DEVELOPED FOR MICROSOFT BY INTEL CORP., HILLSBORO, OREGON **
** HTTP://WWW.INTEL.COM/ **
** THIS FILE IS PART OF THE INTEL ETHEREXPRESS PRO/100B(TM) AND **
** ETHEREXPRESS PRO/100+(TM) NDIS 5.0 MINIPORT SAMPLE DRIVER **
****************************************************************************/
#if !defined(AFX_E100BEXHW_H__0E5098AF_1538_11D4_AFF3_00C04F6A5DA9__INCLUDED_)
#define AFX_E100BEXHW_H__0E5098AF_1538_11D4_AFF3_00C04F6A5DA9__INCLUDED_
#if _MSC_VER > 1000
#pragma once
#endif // _MSC_VER > 1000
//-------------------------------------------------------------------------
// Ethernet Frame Sizes
//-------------------------------------------------------------------------
const USHORT ETHERNET_ADDRESS_LENGTH = 6;
const USHORT ETHERNET_HEADER_SIZE = 14;
const USHORT MINIMUM_ETHERNET_PACKET_SIZE = 60;
const USHORT MAXIMUM_ETHERNET_PACKET_SIZE = 1514;
const USHORT MAX_MULTICAST_ADDRESSES = 32;
const USHORT TCB_BUFFER_SIZE = 0XE0; // 224
const USHORT COALESCE_BUFFER_SIZE = 2048;
const USHORT ETH_MAX_COPY_LENGTH = 0x80; // 128
const USHORT RCB_BUFFER_SIZE = 1520; // 0x5F0
//- Area reserved for all Non Transmit command blocks
const USHORT MAX_NON_TX_CB_AREA = 512;
//-------------------------------------------------------------------------
// Ndis/Adapter driver constants
//-------------------------------------------------------------------------
const UCHAR MAX_PHYS_DESC = 16;
const USHORT MAX_RECEIVE_DESCRIPTORS = 1024; // 0x400
const UCHAR NUM_RMD = 10;
const UCHAR MAX_NUM_ALLOCATED_RFDS = 64;
const UCHAR MIN_NUM_RFD = 4;
const UCHAR MAX_ARRAY_SEND_PACKETS = 8;
// limit our receive routine to indicating this many at a time
const UCHAR MAX_ARRAY_RECEIVE_PACKETS = 16;
const ULONG DRIVER_NULL = 0xffffffff;
const ULONG DRIVER_ZERO = 0;
//-------------------------------------------------------------------------
// Bit Mask definitions
//-------------------------------------------------------------------------
const USHORT BIT_0 = 0x0001;
const USHORT BIT_1 = 0x0002;
const USHORT BIT_2 = 0x0004;
const USHORT BIT_3 = 0x0008;
const USHORT BIT_4 = 0x0010;
const USHORT BIT_5 = 0x0020;
const USHORT BIT_6 = 0x0040;
const USHORT BIT_7 = 0x0080;
const USHORT BIT_8 = 0x0100;
const USHORT BIT_9 = 0x0200;
const USHORT BIT_10 = 0x0400;
const USHORT BIT_11 = 0x0800;
const USHORT BIT_12 = 0x1000;
const USHORT BIT_13 = 0x2000;
const USHORT BIT_14 = 0x4000;
const USHORT BIT_15 = 0x8000;
const ULONG BIT_24 = 0x01000000;
const ULONG BIT_28 = 0x10000000;
const ULONG BIT_29 = 0x20000000;
const USHORT BIT_0_2 = 0x0007;
const USHORT BIT_0_3 = 0x000F;
const USHORT BIT_0_4 = 0x001F;
const USHORT BIT_0_5 = 0x003F;
const USHORT BIT_0_6 = 0x007F;
const USHORT BIT_0_7 = 0x00FF;
const USHORT BIT_0_8 = 0x01FF;
const USHORT BIT_0_13 = 0x3FFF;
const USHORT BIT_0_15 = 0xFFFF;
const USHORT BIT_1_2 = 0x0006;
const USHORT BIT_1_3 = 0x000E;
const USHORT BIT_2_5 = 0x003C;
const USHORT BIT_3_4 = 0x0018;
const USHORT BIT_4_5 = 0x0030;
const USHORT BIT_4_6 = 0x0070;
const USHORT BIT_4_7 = 0x00F0;
const USHORT BIT_5_7 = 0x00E0;
const USHORT BIT_5_9 = 0x03E0;
const USHORT BIT_5_12 = 0x1FE0;
const USHORT BIT_5_15 = 0xFFE0;
const USHORT BIT_6_7 = 0x00c0;
const USHORT BIT_7_11 = 0x0F80;
const USHORT BIT_8_10 = 0x0700;
const USHORT BIT_9_13 = 0x3E00;
const USHORT BIT_12_15 = 0xF000;
const ULONG BIT_16_20 = 0x001F0000;
const ULONG BIT_21_25 = 0x03E00000;
const ULONG BIT_26_27 = 0x0C000000;
//-------------------------------------------------------------------------
// D100 Stepping Defines
//-------------------------------------------------------------------------
const USHORT D100_A_STEP = 0; // NEVER SHIPPED
const USHORT D100_B_STEP = 1; // d100 first shipped silicon
const USHORT D100_C_STEP = 2; // d100' (c-step) with vendor/id and hw fix
const USHORT D101_A_STEP = 4; // first silicon of d101
//-------------------------------------------------------------------------
// D100 PORT functions -- lower 4 bits
//-------------------------------------------------------------------------
const USHORT PORT_SOFTWARE_RESET = 0;
const USHORT PORT_SELFTEST = 1;
const USHORT PORT_SELECTIVE_RESET = 2;
const USHORT PORT_DUMP = 3;
//-------------------------------------------------------------------------
// CSR field definitions -- Offsets from CSR base
//-------------------------------------------------------------------------
const USHORT SCB_STATUS_LOW_BYTE = 0x0;
const USHORT SCB_STATUS_HIGH_BYTE = 0x1;
const USHORT SCB_COMMAND_LOW_BYTE = 0x2;
const USHORT SCB_COMMAND_HIGH_BYTE = 0x3;
const USHORT SCB_GENERAL_POINTER = 0x4;
const USHORT CSR_PORT_LOW_WORD = 0x8;
const USHORT CSR_PORT_HIGH_WORD = 0x0a;
const USHORT CSR_FLASH_CONTROL_REG = 0x0c;
const USHORT CSR_EEPROM_CONTROL_REG = 0x0e;
const USHORT CSR_MDI_CONTROL_LOW_WORD = 0x10;
const USHORT CSR_MDI_CONTROL_HIGH_WORD = 0x12;
//-------------------------------------------------------------------------
// SCB Status Word bit definitions
//-------------------------------------------------------------------------
//- Interrupt status fields
const USHORT SCB_STATUS_MASK = BIT_12_15; // ACK Mask
const USHORT SCB_STATUS_CX = BIT_15; // CU Completed Action Cmd
const USHORT SCB_STATUS_FR = BIT_14; // RU Received A Frame
const USHORT SCB_STATUS_CNA = BIT_13; // CU Became Inactive (IDLE)
const USHORT SCB_STATUS_RNR = BIT_12; // RU Became Not Ready
const USHORT SCB_STATUS_MDI = BIT_11; // MDI read or write done
const USHORT SCB_STATUS_SWI = BIT_10; // Software generated interrupt
//- Interrupt ACK fields
const USHORT SCB_ACK_MASK = BIT_9 | BIT_12_15; // ACK Mask
const USHORT SCB_ACK_CX = BIT_15; // CU Completed Action Cmd
const USHORT SCB_ACK_FR = BIT_14; // RU Received A Frame
const USHORT SCB_ACK_CNA = BIT_13; // CU Became Inactive (IDLE)
const USHORT SCB_ACK_RNR = BIT_12; // RU Became Not Ready
const USHORT SCB_ACK_MDI = BIT_11; // MDI read or write done
const USHORT SCB_ACK_SWI = BIT_10; // Software generated interrupt
const USHORT SCB_ACK_ER = BIT_9; // Early Receive interrupt
//- CUS Fields
const USHORT SCB_CUS_MASK = BIT_6 | BIT_7; // CUS 2-bit Mask
const USHORT SCB_CUS_IDLE = 0; // CU Idle
const USHORT SCB_CUS_SUSPEND = BIT_6; // CU Suspended
const USHORT SCB_CUS_ACTIVE = BIT_7; // CU Active
//- RUS Fields
const USHORT SCB_RUS_IDLE = 0; // RU Idle
const USHORT SCB_RUS_MASK = BIT_2_5; // RUS 3-= BIT Mask
const USHORT SCB_RUS_SUSPEND = BIT_2; // RU Suspended
const USHORT SCB_RUS_NO_RESOURCES = BIT_3; // RU Out Of Resources
const USHORT SCB_RUS_READY = BIT_4; // RU Ready
const USHORT SCB_RUS_SUSP_NO_RBDS = BIT_2 | BIT_5; // RU No More RBDs
const USHORT SCB_RUS_NO_RBDS = BIT_3 | BIT_5; // RU No More RBDs
const USHORT SCB_RUS_READY_NO_RBDS = BIT_4 | BIT_5; // RU Ready, No RBDs
//-------------------------------------------------------------------------
// SCB Command Word bit definitions
//-------------------------------------------------------------------------
//- CUC fields
const USHORT SCB_CUC_MASK = BIT_4_6; // CUC 3-= BIT Mask
const USHORT SCB_CUC_START = BIT_4; // CU Start
const USHORT SCB_CUC_RESUME = BIT_5; // CU Resume
const USHORT SCB_CUC_DUMP_ADDR = BIT_6; // CU Dump Counters Address
const USHORT SCB_CUC_DUMP_STAT = BIT_4 | BIT_6; // CU Dump statistics counters
const USHORT SCB_CUC_LOAD_BASE = BIT_5 | BIT_6; // Load the CU base
const USHORT SCB_CUC_DUMP_RST_STAT = BIT_4_6; // CU Dump and reset statistics counters
const USHORT SCB_CUC_STATIC_RESUME = BIT_5 | BIT_7; // CU Static Resume
//- RUC fields
const USHORT SCB_RUC_MASK = BIT_0_2; // RUC 3-= BIT Mask
const USHORT SCB_RUC_START = BIT_0; // RU Start
const USHORT SCB_RUC_RESUME = BIT_1; // RU Resume
const USHORT SCB_RUC_ABORT = BIT_2; // RU Abort
const USHORT SCB_RUC_LOAD_HDS = BIT_0 | BIT_2; // Load RFD Header Data Size
const USHORT SCB_RUC_LOAD_BASE = BIT_1 | BIT_2; // Load the RU base
const USHORT SCB_RUC_RBD_RESUME = BIT_0_2; // RBD resume
// Interrupt fields (assuming byte addressing)
const USHORT SCB_INT_MASK = BIT_0; // Mask interrupts
const USHORT SCB_SOFT_INT = BIT_1; // Generate a software interrupt
//-------------------------------------------------------------------------
// EEPROM bit definitions
//-------------------------------------------------------------------------
//- EEPROM control register bits
const USHORT EN_TRNF = 0x10; // Enable turnoff
const USHORT EEDO = 0x08; // EEPROM data out
const USHORT EEDI = 0x04; // EEPROM data in (set for writing data)
const USHORT EECS = 0x02; // EEPROM chip select (1=high, 0=low)
const USHORT EESK = 0x01; // EEPROM shift clock (1=high, 0=low)
//- EEPROM opcodes
const USHORT EEPROM_READ_OPCODE = 06;
const USHORT EEPROM_WRITE_OPCODE = 05;
const USHORT EEPROM_ERASE_OPCODE = 07;
const USHORT EEPROM_EWEN_OPCODE = 19; // Erase/write enable
const USHORT EEPROM_EWDS_OPCODE = 16; // Erase/write disable
//- EEPROM data locations
const USHORT EEPROM_NODE_ADDRESS_BYTE_0 = 0;
const USHORT EEPROM_FLAGS_WORD_3 = 3;
const USHORT EEPROM_FLAG_10MC = BIT_0;
const USHORT EEPROM_FLAG_100MC = BIT_1;
//-------------------------------------------------------------------------
// D100 Action Commands
//-------------------------------------------------------------------------
const USHORT CB_NOP = 0;
const USHORT CB_IA_ADDRESS = 1;
const USHORT CB_CONFIGURE = 2;
const USHORT CB_MULTICAST = 3;
const USHORT CB_TRANSMIT = 4;
const USHORT CB_LOAD_MICROCODE = 5;
const USHORT CB_DUMP = 6;
const USHORT CB_DIAGNOSE = 7;
//-------------------------------------------------------------------------
// Command Block (CB) Field Definitions
//-------------------------------------------------------------------------
//- CB Command Word
const USHORT CB_EL_BIT = BIT_15; // CB EL Bit
const USHORT CB_S_BIT = BIT_14; // CB Suspend Bit
const USHORT CB_I_BIT = BIT_13; // CB Interrupt Bit
const USHORT CB_TX_SF_BIT = BIT_3; // TX CB Flexible Mode
const USHORT CB_CMD_MASK = BIT_0_2; // CB 3-bit CMD Mask
//- CB Status Word
const USHORT CB_STATUS_MASK = BIT_12_15; // CB Status Mask (4-bits)
const USHORT CB_STATUS_COMPLETE = BIT_15; // CB Complete Bit
const USHORT CB_STATUS_OK = BIT_13; // CB OK Bit
const USHORT CB_STATUS_UNDERRUN = BIT_12; // CB A Bit
const USHORT CB_STATUS_FAIL = BIT_11; // CB Fail (F) Bit
//misc command bits
const USHORT CB_TX_EOF_BIT = BIT_15; // TX CB/TBD EOF Bit
//-------------------------------------------------------------------------
// Config CB Parameter Fields
//-------------------------------------------------------------------------
const USHORT CB_CFIG_BYTE_COUNT = 22; // 22 config bytes
const USHORT CB_SHORT_CFIG_BYTE_COUNT = 8; // 8 config bytes
// byte 0 bit definitions
const USHORT CB_CFIG_BYTE_COUNT_MASK = BIT_0_5; // Byte count occupies bit 5-0
// byte 1 bit definitions
const USHORT CB_CFIG_RXFIFO_LIMIT_MASK = BIT_0_4; // RxFifo limit mask
const USHORT CB_CFIG_TXFIFO_LIMIT_MASK = BIT_4_7; // TxFifo limit mask
// byte 3 bit definitions --
const USHORT CB_CFIG_B3_MWI_ENABLE = BIT_0; // Memory Write Invalidate Enable Bit
// byte 4 bit definitions
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