mcs51reg.h

很少见的源码公开的msc51和z80的c编译器。

// Bit registers
sbit at 0xE8 ECT0	;
sbit at 0xE9 ECT1	;
sbit at 0xEA ECT2	;
sbit at 0xEB ECT3	;
sbit at 0xEC ECM0	;
sbit at 0xED ECM1	;
sbit at 0xEE ECM2	;
sbit at 0xEF ET2	;
#endif

#ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
#undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
sfr at 0xB8 IEN1        ; // interrupt enable register - SAB80515 specific
// Bit registers
sbit at 0xB8 EADC       ; // A/D converter interrupt enable
sbit at 0xB9 EX2        ;
sbit at 0xBA EX3        ;
sbit at 0xBB EX4        ;
sbit at 0xBC EX5        ;
sbit at 0xBD EX6        ;
sbit at 0xBE SWDT       ; // watchdog timer start/reset
sbit at 0xBF EXEN2      ; // timer2 external reload interrupt enable
#endif

#ifdef IEN2__SAB80517
#undef IEN2__SAB80517
sfr at 0x9A IEN2        ; // interrupt enable register 2 SAB80517
#endif

#ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
#undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
sfr at 0xB8 IP   ;
// Bit registers
sbit at 0xB8 PX0  ;
sbit at 0xB9 PT0  ;
sbit at 0xBA PX1  ;
sbit at 0xBB PT1  ;
sbit at 0xBC PS   ;
#endif

#ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
#undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
sfr at 0xB8 IP    ;
// Bit registers
sbit at 0xB8 PX0  ;
sbit at 0xB9 PT0  ;
sbit at 0xBA PX1  ;
sbit at 0xBB PT1  ;
sbit at 0xBC PS   ;
sbit at 0xBC PS0  ;  // alternate name
sbit at 0xBD PT2  ;
#endif

#ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
#undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
sfr at 0xB8 IP		; // Interrupt priority 0, P80C552 specific
sfr at 0xB8 IP0		; // alternate name
// Bit registers
sbit at 0xB8 PX0	;
sbit at 0xB9 PT0	;
sbit at 0xBA PX1	;
sbit at 0xBB PT1	;
sbit at 0xBC PS0	;
sbit at 0xBD PS1	;
sbit at 0xBE PAD	;
#endif

#ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
#undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
sfr at 0xB8 IP   ;
// Bit registers
sbit at 0xB8 PX0  ;
sbit at 0xB9 PT0  ;
sbit at 0xBA PX1  ;
sbit at 0xBB PT1  ;
sbit at 0xBC PS   ;
sbit at 0xBD PT2  ;
sbit at 0xBE PS1  ;
#endif

#ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
#undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
sfr at 0xB8 IP   ;
// Bit registers
sbit at 0xB8 PX0  ;
sbit at 0xB9 PT0  ;
sbit at 0xBA PX1  ;
sbit at 0xBB PT1  ;
sbit at 0xBC PS   ;
sbit at 0xBF RWT  ;
#endif

#ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
#undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
sfr at 0xA9 IP0   ; // interrupt priority register SAB80515 specific
// Not directly accessible IP0 bits
#define IP0_0    0x01
#define IP0_1    0x02
#define IP0_2    0x04
#define IP0_3    0x08
#define IP0_4    0x10
#define IP0_5    0x20
#define WDTS     0x40
#endif

#ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
#undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
sfr at 0xB8 IP0   ; // interrupt priority register DS89C420 specific
// Not directly accessible IP0 bits
#define LPX0    0x01
#define LPT0    0x02
#define LPX1    0x04
#define LPT1    0x08
#define LPS0    0x10
#define LPT2    0x20
#define LPS1    0x40
#endif

#ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
#undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
sfr at 0xB9 IP1   ; // interrupt priority register SAB80515 specific
// Not directly accessible IP1 bits
#define IP1_0    0x01
#define IP1_1    0x02
#define IP1_2    0x04
#define IP1_3    0x08
#define IP1_4    0x10
#define IP1_5    0x20
#endif

#ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
#undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
sfr at 0xB1 IP1   ; // interrupt priority register DS89C420 specific
// Not directly accessible IP0 bits
#define LPX0    0x01
#define LPT0    0x02
#define LPX1    0x04
#define LPT1    0x08
#define LPS0    0x10
#define LPT2    0x20
#define LPS1    0x40
#endif

#ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
#undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
sfr at 0xF8 IP1		; // Interrupt priority 1, P80C552 specific
// Bit registers
sbit at 0xF8 PCT0	;
sbit at 0xF9 PCT1	;
sbit at 0xFA PCT2	;
sbit at 0xFB PCT3	;
sbit at 0xFC PCM0	;
sbit at 0xFD PCM1	;
sbit at 0xFE PCM2	;
sbit at 0xFF PT2	;
#endif

#ifdef IRCON
#undef IRCON
sfr at 0xC0 IRCON       ; // interrupt control register - SAB80515 specific
// Bit registers
sbit at 0xC0 IADC       ; // A/D converter irq flag
sbit at 0xC1 IEX2       ; // external interrupt edge detect flag
sbit at 0xC2 IEX3       ;
sbit at 0xC3 IEX4       ;
sbit at 0xC4 IEX5       ;
sbit at 0xC5 IEX6       ;
sbit at 0xC6 TF2        ; // timer 2 owerflow flag
sbit at 0xC7 EXF2       ; // timer2 reload flag
#endif

#ifdef IRCON0
#undef IRCON0
sfr at 0xC0 IRCON0       ; // interrupt control register - SAB80515 specific
// Bit registers
sbit at 0xC0 IADC       ; // A/D converter irq flag
sbit at 0xC1 IEX2       ; // external interrupt edge detect flag
sbit at 0xC2 IEX3       ;
sbit at 0xC3 IEX4       ;
sbit at 0xC4 IEX5       ;
sbit at 0xC5 IEX6       ;
sbit at 0xC6 TF2        ; // timer 2 owerflow flag
sbit at 0xC7 EXF2       ; // timer2 reload flag
#endif

#ifdef IRCON1
#undef IRCON1
sfr at 0xD1 IRCON1      ; // interrupt control register - SAB80515 specific
#endif

#ifdef MA
#undef MA
sfr at 0xD3 MA          ; // DS80C390
#endif

#ifdef MB
#undef MB
sfr at 0xD4 MB          ; // DS80C390
#endif

#ifdef MC
#undef MC
sfr at 0xD5 MC          ; // DS80C390
#endif

#ifdef MCNT0
#undef MCNT0
sfr at 0xD1 MCNT0       ; // DS80C390
#define MAS0     0x01
#define MAS1     0x02
#define MAS2     0x04
#define MAS3     0x08
#define MAS4     0x10
#define SCB      0x20
#define CSE      0x40
#define LSHIFT   0x80
#endif

#ifdef MCNT1
#undef MCNT1
sfr at 0xD2 MCNT1       ; // DS80C390
#define CLM      0x10
#define MOF      0x40
#define MST      0x80
#endif

#ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
#undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
sfr at 0xC6 MCON        ; // DS80C390
#define PDCE0    0x01
#define PDCE1    0x02
#define PDCE2    0x04
#define PDCE3    0x08
#define CMA      0x20
#define IDM0     0x40
#define IDM1     0x80
#endif

#ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
#undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
sfr at 0xC6 MCON        ; // DS5000
#define SL       0x01
#define PAA      0x02
#define ECE2     0x04
#define RA32_8   0x08
#define PA0      0x10
#define PA1      0x20
#define PA2      0x40
#define PA3      0x80
#endif

#ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
#undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
sfr at 0xC6 MCON        ; // DS5001
#define SL       0x01
#define PM       0x02
#define PES      0x04
#define RG1      0x08
#define PA0      0x10
#define PA1      0x20
#define PA2      0x40
#define PA3      0x80
#endif

#ifdef MD0
#undef MD0
sfr at 0xE9 MD0         ; // MUL / DIV register 0 SAB80517
#endif

#ifdef MD1
#undef MD1
sfr at 0xEA MD1         ; // MUL / DIV register 1 SAB80517
#endif

#ifdef MD2
#undef MD2
sfr at 0xEB MD2         ; // MUL / DIV register 2 SAB80517
#endif

#ifdef MD3
#undef MD3
sfr at 0xEC MD3         ; // MUL / DIV register 3 SAB80517
#endif

#ifdef MD4
#undef MD4
sfr at 0xED MD4         ; // MUL / DIV register 4 SAB80517
#endif

#ifdef MD5
#undef MD5
sfr at 0xEE MD5         ; // MUL / DIV register 5 SAB80517
#endif

#ifdef MXAX
#undef MXAX
sfr at 0xEA MXAX        ; // Dallas DS80C390
#endif

#ifdef P0
#undef P0
sfr at 0x80 P0   ;
//  Bit Registers
sbit at 0x80 P0_0 ;
sbit at 0x81 P0_1 ;
sbit at 0x82 P0_2 ;
sbit at 0x83 P0_3 ;
sbit at 0x84 P0_4 ;
sbit at 0x85 P0_5 ;
sbit at 0x86 P0_6 ;
sbit at 0x87 P0_7 ;
#endif

#ifdef P1
#undef P1
sfr at 0x90 P1   ;
// Bit registers
sbit at 0x90 P1_0 ;
sbit at 0x91 P1_1 ;
sbit at 0x92 P1_2 ;
sbit at 0x93 P1_3 ;
sbit at 0x94 P1_4 ;
sbit at 0x95 P1_5 ;
sbit at 0x96 P1_6 ;
sbit at 0x97 P1_7 ;
#endif

#ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
#undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
// P1 alternate functions
sbit at 0x90 T2   ;
sbit at 0x91 T2EX ;
sbit at 0x92 RXD1 ;
sbit at 0x93 TXD1 ;
sbit at 0x94 INT2 ;
sbit at 0x95 INT3 ;
sbit at 0x96 INT4 ;
sbit at 0x97 INT5 ;
#endif

#ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
sbit at 0x90 INT3_CC0   ; // P1 alternate functions - SAB80515 specific
sbit at 0x91 INT4_CC1   ;
sbit at 0x92 INT5_CC2   ;
sbit at 0x93 INT6_CC3   ;
sbit at 0x94 INT2       ;
sbit at 0x95 T2EX       ;
sbit at 0x96 CLKOUT     ;
sbit at 0x97 T2         ;
#endif

#ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
#undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
// Bit registers
sbit at 0x90 CT0I	; // Port 1 alternate functions, P80C552 specific
sbit at 0x91 CT1I	;
sbit at 0x92 CT2I	;
sbit at 0x93 CT3I	;
sbit at 0x94 T2		;
sbit at 0x95 RT2	;
sbit at 0x96 SCL	;
sbit at 0x97 SDA	;
#endif

#ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
#undef P1_EXT__x__x__x__x__x__x__T2EX__T2
// P1 alternate functions
sbit at 0x90 T2         ;
sbit at 0x91 T2EX       ;
#endif

#ifdef P2
#undef P2
sfr at 0xA0 P2   ;
// Bit registers
sbit at 0xA0 P2_0 ;
sbit at 0xA1 P2_1 ;
sbit at 0xA2 P2_2 ;
sbit at 0xA3 P2_3 ;
sbit at 0xA4 P2_4 ;
sbit at 0xA5 P2_5 ;
sbit at 0xA6 P2_6 ;
sbit at 0xA7 P2_7 ;
#endif

#ifdef P3
#undef P3
sfr at 0xB0 P3   ;
// Bit registers
sbit at 0xB0 P3_0 ;
sbit at 0xB1 P3_1 ;
sbit at 0xB2 P3_2 ;
sbit at 0xB3 P3_3 ;
sbit at 0xB4 P3_4 ;
sbit at 0xB5 P3_5 ;
#ifndef MCS51REG_EXTERNAL_RAM
sbit at 0xB6 P3_6 ;
sbit at 0xB7 P3_7 ;
#endif
// alternate names
sbit at 0xB0 RXD  ;
sbit at 0xB0 RXD0  ;
sbit at 0xB1 TXD  ;
sbit at 0xB1 TXD0  ;
sbit at 0xB2 INT0 ;
sbit at 0xB3 INT1 ;
sbit at 0xB4 T0   ;
sbit at 0xB5 T1   ;
#ifndef MCS51REG_EXTERNAL_RAM
sbit at 0xB6 WR   ;
sbit at 0xB7 RD   ;
#endif
#endif

#ifdef P4_AT_0X80
#undef P4_AT_0X80
sfr at 0x80 P4          ; // Port 4 - DS80C390
// Bit registers
sbit at 0x80 P4_0       ;
sbit at 0x81 P4_1       ;
sbit at 0x82 P4_2       ;
sbit at 0x83 P4_3       ;
sbit at 0x84 P4_4       ;
sbit at 0x85 P4_5       ;
sbit at 0x86 P4_6       ;
sbit at 0x87 P4_7       ;
#endif

#ifdef P4_AT_0XC0
#undef P4_AT_0XC0
sfr at 0xC0 P4		; // Port 4, P80C552 specific
// Bit registers
sbit at 0xC0 CMSR0	;
sbit at 0xC1 CMSR1	;
sbit at 0xC2 CMSR2	;
sbit at 0xC3 CMSR3	;
sbit at 0xC4 CMSR4	;
sbit at 0xC5 CMSR5	;
sbit at 0xC6 CMT0	;
sbit at 0xC7 CMT1	;
#endif

#ifdef P4_AT_0XE8
#undef P4_AT_0XE8
sfr at 0xE8 P4          ; // Port 4 - SAB80515 & compatible microcontrollers
// Bit registers
sbit at 0xE8 P4_0       ;
sbit at 0xE9 P4_1       ;
sbit at 0xEA P4_2       ;
sbit at 0xEB P4_3       ;
sbit at 0xEC P4_4       ;
sbit at 0xED P4_5       ;
sbit at 0xEE P4_6       ;
sbit at 0xEF P4_7       ;
#endif

#ifdef P4CNT
#undef P4CNT
sfr at 0x92 P4CNT       ; // DS80C390
// Not directly accessible bits
#define P4CNT_0  0x01
#define P4CNT_1  0x02
#define P4CNT_2  0x04
#define P4CNT_3  0x08
#define P4CNT_4  0x10
#define P4CNT_5  0x20
#define SBCAN    0x40
#endif

#ifdef P5_AT_0XA1
#undef P5_AT_0XA1
sfr at 0xA1 P5          ; // Port 5 - DS80C390
#endif

#ifdef P5CNT
#undef P5CNT
sfr at 0xA2 P5CNT       ; // DS80C390
// Not directly accessible bits
#define P5CNT_0  0x01
#define P5CNT_1  0x02
#define P5CNT_2  0x04
#define C0_I_O   0x08
#define C1_I_O   0x10
#define SP1EC    0x20
#define SBCAN0BA 0x40
#define SBCAN1BA 0x80
#endif

#ifdef P5_AT_0XC4
#undef P5_AT_0XC4
sfr at 0xC4 P5		; // Port 5, P80C552 specific
// Not directly accessible Bits.
#define ADC0	0x01
#define ADC1	0x02
#define ADC2	0x04
#define ADC3	0x08
#define ADC4	0x10
#define ADC5	0x20
#define ADC6	0x40
#define ADC7	0x80
#endif

#ifdef P5_AT_0XF8
#undef P5_AT_0XF8
sfr at 0xF8 P5          ; // Port 5 - SAB80515 & compatible microcontrollers
// Bit registers
sbit at 0xF8 P5_0       ;
sbit at 0xF9 P5_1       ;
sbit at 0xFA P5_2       ;
sbit at 0xFB P5_3       ;
sbit at 0xFC P5_4       ;
sbit at 0xFD P5_5       ;
sbit at 0xFE P5_6       ;
sbit at 0xFF P5_7       ;
#endif

#ifdef P6_AT_0XDB
#undef P6_AT_0XDB
sfr at 0xDB P6          ; // Port 6 - SAB80515 & compatible microcontrollers
#endif

#ifdef P6_AT_0XFA
#undef P6_AT_0XFA
sfr at 0xFA P6          ; // Port 6 - SAB80517 specific
#endif

#ifdef P7_AT_0XDB
#undef P7_AT_0XDB
sfr at 0xDB P7          ; // Port 7 - SAB80517 specific
#endif

#ifdef P8_AT_0XDD
#undef P8_AT_0XDD
sfr at 0xDD P8          ; // Port 6 - SAB80517 specific
#endif

#ifdef PCON__SMOD__x__x__x__x__x__x__x
#undef PCON__SMOD__x__x__x__x__x__x__x
sfr at 0x87 PCON ;
// Not directly accessible PCON bits
#define SMOD    0x80
#endif

#ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
#undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
sfr at 0x87 PCON ;
// Not directly accessible PCON bits
#define IDL             0x01