📄 mcs51reg.h
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#define ADDAT
#define DAPR__SAB80517
#define P4_AT_0XE8
#define P5_AT_0XF8
#define P6_AT_0XFA
#define P7_AT_0XDB
#define P8_AT_0XDD
#define DPSEL
#define ARCON
#define MD0
#define MD1
#define MD2
#define MD3
#define MD4
#define MD5
#define S0BUF
#define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
#define S0RELH
#define S0RELL
#define S1BUF
#define S1CON_AT_0X9B
#define S1RELH
#define S1RELL
#define WDTH
#define WDTL
#define WDTREL
#endif
// end of definitions for the Infineon / Siemens SAB80517
/////////////////////////////////////////////////////////
/// don't specify microcontrollers below this line! ///
/////////////////////////////////////////////////////////
// default microcontroller -> 8051
// use default if no microcontroller specified
#ifndef MICROCONTROLLER_DEFINED
#define MICROCONTROLLER_DEFINED
#ifdef MCS51REG_ENABLE_WARNINGS
#warning No microcontroller defined!
#warning Code generated for the 8051
#endif
// 8051 register set
#define P0
#define SP
#define DPL
#define DPH
#define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
#define TCON
#define TMOD
#define TL0
#define TL1
#define TH0
#define TH1
#define P1
#define SCON
#define SBUF
#define P2
#define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
#define P3
#define IP__x__x__x__PS__PT1__PX1__PT0__PX0
#define PSW
#define ACC
#define B
#endif
// end of definitions for the default microcontroller
#ifdef MCS51REG_ERROR
#error Two or more microcontrollers defined!
#endif
#ifdef MCS51REG_EXTERNAL_ROM
#ifndef MCS51REG_UNDEFINE_P0
#define MCS51REG_UNDEFINE_P0
#endif
#ifndef MCS51REG_UNDEFINE_P2
#define MCS51REG_UNDEFINE_P2
#endif
#endif
#ifdef MCS51REG_EXTERNAL_RAM
#ifndef MCS51REG_UNDEFINE_P0
#define MCS51REG_UNDEFINE_P0
#endif
#ifndef MCS51REG_UNDEFINE_P2
#define MCS51REG_UNDEFINE_P2
#endif
#endif
#ifdef MCS51REG_UNDEFINE_P0
#undef P0
#endif
#ifdef MCS51REG_UNDEFINE_P2
#undef P2
#endif
////////////////////////////////
/// Register definitions ///
/// (In alphabetical order) ///
////////////////////////////////
#ifdef ACC
#undef ACC
sfr at 0xE0 ACC ;
#endif
#ifdef ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
#undef ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
sfr at 0x9D ACON ; // DS89C420 specific
// Not directly accessible bits
#define PAGE0 0x20
#define PAGES 0x40
#define PAGEE 0x80
#endif
#ifdef ACON__x__x__x__x__x__SA__AM1__AM0
#undef ACON__x__x__x__x__x__SA__AM1__AM0
sfr at 0x9D ACON ; // DS89C390 specific
// Not directly accessible bits
#define AM0 0x01
#define AM1 0x02
#define SA 0x04
#endif
#ifdef ADCH_AT_0XC6
#undef ADCH_AT_0XC6
sfr at 0xC6 ADCH ; // A/D converter high
#endif
#ifdef ADCON
#undef ADCON
sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
// Bit registers
sbit at 0xD8 MX0 ;
sbit at 0xD9 MX1 ;
sbit at 0xDA MX2 ;
sbit at 0xDB ADM ;
sbit at 0xDC BSY ;
sbit at 0xDE CLK ;
sbit at 0xDF BD ;
#endif
// ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
#ifdef ADCON0
#undef ADCON0
sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
// Bit registers // SAB80517 specific
sbit at 0xD8 MX0 ;
sbit at 0xD9 MX1 ;
sbit at 0xDA MX2 ;
sbit at 0xDB ADM ;
sbit at 0xDC BSY ;
sbit at 0xDD ADEX ;
sbit at 0xDE CLK ;
sbit at 0xDF BD ;
// Not directly accessible ADCON0
#define ADCON0_MX0 0x01
#define ADCON0_MX1 0x02
#define ADCON0_MX2 0x04
#define ADCON0_ADM 0x08
#define ADCON0_BSY 0x10
#define ADCON0_ADEX 0x20
#define ADCON0_CLK 0x40
#define ADCON0_BD 0x80
#endif
#ifdef ADCON1
#undef ADCON1
sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
// Not directly accessible ADCON1
#define ADCON1_MX0 0x01
#define ADCON1_MX1 0x02
#define ADCON1_MX2 0x04
#define ADCON1_ADCL 0x80
#endif
#ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
#undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
sfr at 0xC5 ADCON ; // A/D control, P80C552 specific
// Not directly accessible Bits.
#define AADR0 0x01
#define AADR1 0x02
#define AADR2 0x04
#define ADCS 0x08
#define ADCI 0x10
#define ADEX 0x20
#define ADC_0 0x40 // different name as ADC0 in P5
#define ADC_1 0x80 // different name as ADC1 in P5
#endif
#ifdef ADDAT
#undef ADDAT
sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
#endif
#ifdef ADDATH
#undef ADDATH
sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
#endif
#ifdef ADDATL
#undef ADDATL
sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
#endif
#ifdef ARCON
#undef ARCON
sfr at 0xEF ARCON ; // arithmetic control register SAB80517
#endif
#ifdef AP
#undef AP
sfr at 0x9C AP ; // DS80C390
#endif
#ifdef B
#undef B
sfr at 0xF0 B ;
// Bit registers
sbit at 0xF0 BREG_F0 ;
sbit at 0xF1 BREG_F1 ;
sbit at 0xF2 BREG_F2 ;
sbit at 0xF3 BREG_F3 ;
sbit at 0xF4 BREG_F4 ;
sbit at 0xF5 BREG_F5 ;
sbit at 0xF6 BREG_F6 ;
sbit at 0xF7 BREG_F7 ;
#endif
#ifdef BP2
#undef BP2
sfr at 0xC3 BP2 ;
// Not directly accessible bits
#define MS0 0x01
#define MS1 0x02
#define MS2 0x04
#define LB1 0x08
#define LB2 0x10
#define LB3 0x20
#endif
#ifdef C0C
#undef C0C
sfr at 0xA3 C0C ; // DS80C390 specific
// Not directly accessible bits
#define SWINT 0x01
#define ERCS 0x02
#define AUTOB 0x04
#define CRST 0x08
#define SIESTA 0x10
#define PDE 0x20
#define STIE 0x40
#define ERIE 0x80
#endif
#ifdef C0IR
#undef C0IR
sfr at 0xA5 C0IR ; // DS80C390 specific
// Not directly accessible bits
#define INTIN0 0x01
#define INTIN1 0x02
#define INTIN2 0x04
#define INTIN3 0x08
#define INTIN4 0x10
#define INTIN5 0x20
#define INTIN6 0x40
#define INTIN7 0x80
#endif
#ifdef C0M1C
#undef C0M1C
sfr at 0xAB C0M1C ; // DS80C390 specific
// Not directly accessible bits
#define DTUP 0x01
#define ROW_TIH 0x02
#define MTRQ 0x04
#define EXTRQ 0x08
#define INTRQ 0x10
#define ERI 0x20
#define ETI 0x40
#define MSRDY 0x80
#endif
#ifdef C0M2C
#undef C0M2C
sfr at 0xAC C0M2C ; // DS80C390 specific
#endif
#ifdef C0M3C
#undef C0M3C
sfr at 0xAD C0M3C ; // DS80C390 specific
#endif
#ifdef C0M4C
#undef C0M4C
sfr at 0xAE C0M4C ; // DS80C390 specific
#endif
#ifdef C0M5C
#undef C0M5C
sfr at 0xAF C0M5C ; // DS80C390 specific
#endif
#ifdef C0M6C
#undef C0M6C
sfr at 0xB3 C0M6C ; // DS80C390 specific
#endif
#ifdef C0M7C
#undef C0M7C
sfr at 0xB4 C0M7C ; // DS80C390 specific
#endif
#ifdef C0M8C
#undef C0M8C
sfr at 0xB5 C0M8C ; // DS80C390 specific
#endif
#ifdef C0M9C
#undef C0M9C
sfr at 0xB6 C0M9C ; // DS80C390 specific
#endif
#ifdef C0M10C
#undef C0M10C
sfr at 0xB7 C0M10C ; // DS80C390 specific
#endif
#ifdef C0M11C
#undef C0M11C
sfr at 0xBB C0M11C ; // DS80C390 specific
#endif
#ifdef C0M12C
#undef C0M12C
sfr at 0xBC C0M12C ; // DS80C390 specific
#endif
#ifdef C0M13C
#undef C0M13C
sfr at 0xBD C0M13C ; // DS80C390 specific
#endif
#ifdef C0M14C
#undef C0M14C
sfr at 0xBE C0M14C ; // DS80C390 specific
#endif
#ifdef C0M15C
#undef C0M15C
sfr at 0xBF C0M15C ; // DS80C390 specific
#endif
#ifdef C0RE
#undef C0RE
sfr at 0xA7 C0RE ; // DS80C390 specific
#endif
#ifdef C0RMS0
#undef C0RMS0
sfr at 0x96 C0RMS0 ; // DS80C390 specific
#endif
#ifdef C0RMS1
#undef C0RMS1
sfr at 0x97 C0RMS1 ; // DS80C390 specific
#endif
#ifdef C0S
#undef C0S
sfr at 0xA4 C0S ; // DS80C390 specific
// Not directly accessible bits
#define ER0 0x01
#define ER1 0x02
#define ER2 0x04
#define TXS 0x08
#define RXS 0x10
#define WKS 0x20
#define EC96_128 0x40
#define BSS 0x80
#endif
#ifdef C0TE
#undef C0TE
sfr at 0xA6 C0TE ; // DS80C390 specific
#endif
#ifdef C0TMA0
#undef C0TMA0
sfr at 0x9E C0TMA0 ; // DS80C390 specific
#endif
#ifdef C0TMA1
#undef C0TMA1
sfr at 0x9F C0TMA1 ; // DS80C390 specific
#endif
#ifdef C1C
#undef C1C
sfr at 0xE3 C1C ; // DS80C390 specific
// Not directly accessible bits
#define SWINT 0x01
#define ERCS 0x02
#define AUTOB 0x04
#define CRST 0x08
#define SIESTA 0x10
#define PDE 0x20
#define STIE 0x40
#define ERIE 0x80
#endif
#ifdef C1IR
#undef C1IR
sfr at 0xE5 C1IR ; // DS80C390 specific
// Not directly accessible bits
#define INTIN0 0x01
#define INTIN1 0x02
#define INTIN2 0x04
#define INTIN3 0x08
#define INTIN4 0x10
#define INTIN5 0x20
#define INTIN6 0x40
#define INTIN7 0x80
#endif
#ifdef C1IRE
#undef C1IRE
sfr at 0xE7 C1RE ; // DS80C390 specific
#endif
#ifdef C1M1C
#undef C1M1C
sfr at 0xEB C1M1C ; // DS80C390 specific
#endif
#ifdef C1M2C
#undef C1M2C
sfr at 0xEC C1M2C ; // DS80C390 specific
#endif
#ifdef C1M3C
#undef C1M3C
sfr at 0xED C1M3C ; // DS80C390 specific
#endif
#ifdef C1M4C
#undef C1M4C
sfr at 0xEE C1M4C ; // DS80C390 specific
#endif
#ifdef C1M5C
#undef C1M5C
sfr at 0xEF C1M5C ; // DS80C390 specific
#endif
#ifdef C1M6C
#undef C1M6C
sfr at 0xF3 C1M6C ; // DS80C390 specific
#endif
#ifdef C1M7C
#undef C1M7C
sfr at 0xF4 C1M7C ; // DS80C390 specific
#endif
#ifdef C1M8C
#undef C1M8C
sfr at 0xF5 C1M8C ; // DS80C390 specific
#endif
#ifdef C1M9C
#undef C1M9C
sfr at 0xF6 C1M9C ; // DS80C390 specific
#endif
#ifdef C1M10C
#undef C1M10C
sfr at 0xF7 C1M10C ; // DS80C390 specific
#endif
#ifdef C1M11C
#undef C1M11C
sfr at 0xFB C1M11C ; // DS80C390 specific
#endif
#ifdef C1M12C
#undef C1M12C
sfr at 0xFC C1M12C ; // DS80C390 specific
#endif
#ifdef C1M13C
#undef C1M13C
sfr at 0xFD C1M13C ; // DS80C390 specific
#endif
#ifdef C1M14C
#undef C1M14C
sfr at 0xFE C1M14C ; // DS80C390 specific
#endif
#ifdef C1M15C
#undef C1M15C
sfr at 0xFF C1M15C ; // DS80C390 specific
#endif
#ifdef C1S
#undef C1S
sfr at 0xE4 C1S ; // DS80C390 specific
// Not directly accessible bits
#define ER0 0x01
#define ER1 0x02
#define ER2 0x04
#define TXS 0x08
#define RXS 0x10
#define WKS 0x20
#define CECE 0x40
#define BSS 0x80
#endif
#ifdef C1ITE
#undef C1ITE
sfr at 0xE6 C1TE ; // DS80C390 specific
#endif
#ifdef C1RSM0
#undef C1RSM0
sfr at 0xD6 C1RSM0 ; // DS80C390 specific
#endif
#ifdef C1RSM1
#undef C1RSM1
sfr at 0xD7 C1RSM1 ; // DS80C390 specific
#endif
#ifdef C1TMA0
#undef C1TMA0
sfr at 0xDE C1TMA0 ; // DS80C390 specific
#endif
#ifdef C1TMA1
#undef C1TMA1
sfr at 0xDF C1TMA1 ; // DS80C390 specific
#endif
#ifdef CC4EN
#undef CC4EN
sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
#endif
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