_modulong.asm

很少见的源码公开的msc51和z80的c编译器。

;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.3.0 Thu Sep 20 10:57:38 2001

;--------------------------------------------------------
	.module _modulong
	
.flat24 on		; 24 bit flat addressing
dpx = 0x93		; dpx register unknown to assembler
dps = 0x86		; dps register unknown to assembler
dpl1 = 0x84		; dpl1 register unknown to assembler
dph1 = 0x85		; dph1 register unknown to assembler
dpx1 = 0x95		; dpx1 register unknown to assembler
ap = 0x9C		; ap register unknown to assembler
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl __modulong_PARM_2
	.globl __modulong
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; special function bits 
;--------------------------------------------------------
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
;--------------------------------------------------------
; overlayable items in internal ram 
;--------------------------------------------------------
	.area OSEG    (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
	.area ISEG    (DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
	.area BSEG    (BIT)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
	.area XSEG    (XDATA)
__modulong_PARM_2::
	.ds 4
__modulong_count_1_1::
	.ds 1
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME	 (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
;	_modulong.c 29
;	genFunction 
;	-----------------------------------------
;	 function _modulong
;	-----------------------------------------
__modulong:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
;	_modulong.c 51
;	genReceive 
	mov	r2,dpl
	mov	r3,dph
	mov	r4,dpx
	mov	r5,b
;	_modulong.c 31
;	genAssign 
;	genAssign: resultIsFar = TRUE
	mov	dptr,#__modulong_count_1_1
; Peephole 180   changed mov to clr
;	_modulong.c 34
;	genAssign 
;	genAssign: resultIsFar = TRUE
; Peephole 180   changed mov to clr
; Peephole 219 removed redundant clear
	clr   a
	movx  @dptr,a
	mov   dptr,#__modulong_count_1_1
	movx  @dptr,a
;	genLabel 
00103$:
	mov	dptr,#__modulong_PARM_2
;	genGetHbit 
	inc	dptr
	inc	dptr
	inc	dptr
	movx	a,@dptr
	rl	a
	anl	a,#0x01
;	genIfx 
; Peephole 105   removed redundant mov
	mov  r0,a
;	genIfxJump 
	jz	00119$
	ljmp	00117$
00119$:
;	_modulong.c 35
;	genLeftShift 
;	genLeftShiftLiteral (1), size 4
;	genLeftShiftLiteral wimping out
	mov	b,#0x02
	mov	dptr,#__modulong_PARM_2
	movx	a,@dptr
	mov	r0,acc
	inc	dptr
	movx	a,@dptr
	mov	r1,acc
	inc	dptr
	movx	a,@dptr
	mov	r6,acc
	inc	dptr
	movx	a,@dptr
	mov	r7,acc
	sjmp	00121$
00120$:
	mov	a,r0
	add	a,acc
	mov	r0,a
	mov	a,r1
	rlc	a
	mov	r1,a
	mov	a,r6
	rlc	a
	mov	r6,a
	mov	a,r7
	rlc	a
	mov	r7,a
00121$:
	djnz	b,00120$
;	genAssign 
;	genAssign: resultIsFar = TRUE
	mov	dptr,#__modulong_PARM_2
	mov	a,r0
	movx	@dptr,a
	inc	dptr
	mov	a,r1
	movx	@dptr,a
	inc	dptr
	mov	a,r6
	movx	@dptr,a
	inc	dptr
	mov	a,r7
	movx	@dptr,a
;	_modulong.c 36
;	genCmpGt 
;	genCmp
	clr	c
;	genCmp #1: 3/0/0
	mov	a,r2
;	genCmp #2
;	genCmp #4
;	genCmp #4.2
	subb	a,r0
;	genCmp #1: 2/0/1
	mov	a,r3
;	genCmp #2
;	genCmp #4
;	genCmp #4.2
	subb	a,r1
;	genCmp #1: 1/0/2
	mov	a,r4
;	genCmp #2
;	genCmp #4
;	genCmp #4.2
	subb	a,r6
;	genCmp #1: 0/0/3
	mov	a,r5
;	genCmp #2
;	genCmp #4
;	genCmp #4.2
	subb	a,r7
;	genIfxJump 
; Peephole 108   removed ljmp by inverse jump logic
	jnc  00102$
00122$:
;	_modulong.c 38
;	genRightShift 
;	genRightShiftLiteral (1), size 4
;	genRightShiftLiteral wimping out
	mov	b,#0x02
	sjmp	00124$
00123$:
	clr	c
	mov	a,r7
	rrc	a
	mov	r7,a
	mov	a,r6
	rrc	a
	mov	r6,a
	mov	a,r1
	rrc	a
	mov	r1,a
	mov	a,r0
	rrc	a
	mov	r0,a
00124$:
	djnz	b,00123$
;	genAssign 
;	genAssign: resultIsFar = TRUE
	mov	dptr,#__modulong_PARM_2
	mov	a,r0
	movx	@dptr,a
	inc	dptr
	mov	a,r1
	movx	@dptr,a
	inc	dptr
	mov	a,r6
	movx	@dptr,a
	inc	dptr
	mov	a,r7
	movx	@dptr,a
;	_modulong.c 39
;	genGoto 
;	genLabel 
; Peephole 132   changed ljmp to sjmp
	sjmp 00117$
00102$:
;	_modulong.c 41
;	genPlus 
	mov	dptr,#__modulong_count_1_1
;	Swapped plus args.
	movx	a,@dptr
	add	a,#0x01
	movx	@dptr,a
;	genAssign 
	mov	dptr,#__modulong_count_1_1
;	genAssign: resultIsFar = TRUE
;	genFarFarAssign (1 byte case)
	movx	a,@dptr
	mov	dptr,#__modulong_count_1_1
	movx	@dptr,a
;	genGoto 
	ljmp	00103$
;	_modulong.c 44
;	genLabel 
00117$:
;	genAssign 
	mov	dptr,#__modulong_count_1_1
;	genAssign: resultIsFar = TRUE
;	genFarFarAssign (1 byte case)
	movx	a,@dptr
	mov	dptr,#__modulong_count_1_1
	movx	@dptr,a
;	genLabel 
00108$:
;	_modulong.c 45
;	genCmpGt 
	mov	dptr,#__modulong_PARM_2
;	genCmp
	clr	c
;	genCmp #1: 3/0/0
	mov	a,r2
;	genCmp #2
;	genCmp #4
;	genCmp #4.1
	xch	a, b
	movx	a,@dptr
	xch	a, b
	subb	a,b
;	genCmp #1: 2/0/1
	mov	a,r3
;	genCmp #2
;	genCmp #4
;	genCmp #4.1
	xch	a, b
	inc	dptr
	movx	a,@dptr
	xch	a, b
	subb	a,b
;	genCmp #1: 1/0/2
	mov	a,r4
;	genCmp #2
;	genCmp #4
;	genCmp #4.1
	xch	a, b
	inc	dptr
	movx	a,@dptr
	xch	a, b
	subb	a,b
;	genCmp #1: 0/0/3
	mov	a,r5
;	genCmp #2
;	genCmp #4
;	genCmp #4.1
	xch	a, b
	inc	dptr
	movx	a,@dptr
	xch	a, b
	subb	a,b
;	genIfxJump 
; Peephole 132   changed ljmp to sjmp
; Peephole 160   removed sjmp by inverse jump logic
	jc   00107$
00125$:
;	_modulong.c 46
;	genMinus 
	mov	dps, #0x01
	mov	dptr, #__modulong_PARM_2
	dec	dps
	clr	c
	mov	a,r2
	xch	a, ap
	inc	dps
	movx	a,@dptr
	xch	a, ap
	subb	a,ap
	mov	r7,a
	mov	a,r3
	xch	a, ap
	inc	dptr
	movx	a,@dptr
	xch	a, ap
	subb	a,ap
	mov	r0,a
	mov	a,r4
	xch	a, ap
	inc	dptr
	movx	a,@dptr
	xch	a, ap
	subb	a,ap
	mov	r1,a
	mov	a,r5
	xch	a, ap
	inc	dptr
	movx	a,@dptr
	xch	a, ap
	subb	a,ap
	mov	r6,a
	mov	dps, #0x00
;	genAssign 
;	genAssign: resultIsFar = TRUE
	mov	ar2,r7
	mov	ar3,r0
	mov	ar4,r1
	mov	ar5,r6
;	genLabel 
00107$:
;	_modulong.c 48
;	genRightShift 
;	genRightShiftLiteral (1), size 4
;	genRightShiftLiteral wimping out
	mov	b,#0x02
	mov	dptr,#__modulong_PARM_2
	movx	a,@dptr
	mov	r6,acc
	inc	dptr
	movx	a,@dptr
	mov	r7,acc
	inc	dptr
	movx	a,@dptr
	mov	r0,acc
	inc	dptr
	movx	a,@dptr
	mov	r1,acc
	sjmp	00127$
00126$:
	clr	c
	mov	a,r1
	rrc	a
	mov	r1,a
	mov	a,r0
	rrc	a
	mov	r0,a
	mov	a,r7
	rrc	a
	mov	r7,a
	mov	a,r6
	rrc	a
	mov	r6,a
00127$:
	djnz	b,00126$
;	genAssign 
;	genAssign: resultIsFar = TRUE
	mov	dptr,#__modulong_PARM_2
	mov	a,r6
	movx	@dptr,a
	inc	dptr
	mov	a,r7
	movx	@dptr,a
	inc	dptr
	mov	a,r0
	movx	@dptr,a
	inc	dptr
	mov	a,r1
	movx	@dptr,a
;	_modulong.c 49
;	genAssign 
	mov	dptr,#__modulong_count_1_1
;	genAssign: resultIsFar = FALSE
	movx	a,@dptr
	mov	r6,a
;	genMinus 
	mov	dptr,#__modulong_count_1_1
	movx	a,@dptr
	dec	a
	movx	@dptr,a
;	genIfx 
	mov	a,r6
;	genIfxJump 
	jz	00128$
	ljmp	00108$
00128$:
;	_modulong.c 51
;	genRet 
	mov	dpl,r2
	mov	dph,r3
	mov	dpx,r4
	mov	b,r5
;	genLabel 
00111$:
;	genEndFunction 
	ret
	.area CSEG    (CODE)