_divulong.asm

很少见的源码公开的msc51和z80的c编译器。

;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.3.0 Thu Sep 20 10:57:33 2001

;--------------------------------------------------------
	.module _divulong
	
.flat24 on		; 24 bit flat addressing
dpx = 0x93		; dpx register unknown to assembler
dps = 0x86		; dps register unknown to assembler
dpl1 = 0x84		; dpl1 register unknown to assembler
dph1 = 0x85		; dph1 register unknown to assembler
dpx1 = 0x95		; dpx1 register unknown to assembler
ap = 0x9C		; ap register unknown to assembler
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl __divulong_PARM_2
	.globl __divulong
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; special function bits 
;--------------------------------------------------------
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
;--------------------------------------------------------
; overlayable items in internal ram 
;--------------------------------------------------------
	.area OSEG    (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
	.area ISEG    (DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
	.area BSEG    (BIT)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
	.area XSEG    (XDATA)
__divulong_PARM_2::
	.ds 4
__divulong_reste_1_1::
	.ds 4
__divulong_count_1_1::
	.ds 1
__divulong_c_1_1::
	.ds 1
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME	 (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
;	_divulong.c 27
;	genFunction 
;	-----------------------------------------
;	 function _divulong
;	-----------------------------------------
__divulong:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
;	_divulong.c 48
;	genReceive 
	mov	r2,dpl
	mov	r3,dph
	mov	r4,dpx
	mov	r5,b
;	_divulong.c 29
;	genAssign 
;	genAssign: resultIsFar = TRUE
	mov	dptr,#__divulong_reste_1_1
	clr	a
	movx	@dptr,a
	inc	dptr
	movx	@dptr,a
	inc	dptr
	movx	@dptr,a
	inc	dptr
	movx	@dptr,a
;	_divulong.c 33
;	genAssign 
;	genAssign: resultIsFar = TRUE
	mov	dptr,#__divulong_count_1_1
	mov	a,#0x20
	movx	@dptr,a
;	genLabel 
00105$:
;	_divulong.c 35
	mov	dptr,#__divulong_c_1_1
;	genGetHbit 
	mov	a,r5
	rl	a
	anl	a,#0x01
	movx	@dptr,a
;	_divulong.c 36
;	genLeftShift 
;	genLeftShiftLiteral (1), size 4
;	genLeftShiftLiteral wimping out
	mov	b,#0x02
	mov	r6,ar2
	mov	r7,ar3
	mov	r0,ar4
	mov	r1,ar5
	sjmp	00115$
00114$:
	mov	a,r6
	add	a,acc
	mov	r6,a
	mov	a,r7
	rlc	a
	mov	r7,a
	mov	a,r0
	rlc	a
	mov	r0,a
	mov	a,r1
	rlc	a
	mov	r1,a
00115$:
	djnz	b,00114$
;	genAssign 
;	genAssign: resultIsFar = TRUE
	mov	ar2,r6
	mov	ar3,r7
	mov	ar4,r0
	mov	ar5,r1
;	_divulong.c 37
;	genLeftShift 
;	genLeftShiftLiteral (1), size 4
;	genLeftShiftLiteral wimping out
	mov	b,#0x02
	mov	dptr,#__divulong_reste_1_1
	movx	a,@dptr
	mov	r6,acc
	inc	dptr
	movx	a,@dptr
	mov	r7,acc
	inc	dptr
	movx	a,@dptr
	mov	r0,acc
	inc	dptr
	movx	a,@dptr
	mov	r1,acc
	sjmp	00117$
00116$:
	mov	a,r6
	add	a,acc
	mov	r6,a
	mov	a,r7
	rlc	a
	mov	r7,a
	mov	a,r0
	rlc	a
	mov	r0,a
	mov	a,r1
	rlc	a
	mov	r1,a
00117$:
	djnz	b,00116$
;	genAssign 
;	genAssign: resultIsFar = TRUE
	mov	dptr,#__divulong_reste_1_1
	mov	a,r6
	movx	@dptr,a
	inc	dptr
	mov	a,r7
	movx	@dptr,a
	inc	dptr
	mov	a,r0
	movx	@dptr,a
	inc	dptr
	mov	a,r1
	movx	@dptr,a
;	_divulong.c 38
;	genIfx 
	mov	dptr,#__divulong_c_1_1
	movx	a,@dptr
;	genIfxJump 
; Peephole 110   removed ljmp by inverse jump logic
	jz  00102$
00118$:
;	_divulong.c 39
;	genOr 
	mov	dptr,#__divulong_reste_1_1
	movx	a,@dptr
	orl	a,#0x01
	movx	@dptr,a
	inc	dptr
	movx	a,@dptr
	orl	a,#0x00
	movx	@dptr,a
	inc	dptr
	movx	a,@dptr
	orl	a,#0x00
	movx	@dptr,a
	inc	dptr
	movx	a,@dptr
	orl	a,#0x00
	movx	@dptr,a
;	genLabel 
00102$:
;	_divulong.c 41
;	genCmpLt 
	mov	dptr,#__divulong_PARM_2
	mov	dps, #0x01
	mov	dptr, #__divulong_reste_1_1
	dec	dps
;	genCmp
	clr	c
;	genCmp #1: 3/0/0
	mov	dps, #0x01
	movx	a,@dptr
	mov	dps, #0x00
;	genCmp #2
;	genCmp #4
;	genCmp #4.1
	xch	a, b
	movx	a,@dptr
	xch	a, b
	subb	a,b
;	genCmp #1: 2/0/1
	mov	dps, #0x01
	inc	dptr
	movx	a,@dptr
	mov	dps, #0x00
;	genCmp #2
;	genCmp #4
;	genCmp #4.1
	xch	a, b
	inc	dptr
	movx	a,@dptr
	xch	a, b
	subb	a,b
;	genCmp #1: 1/0/2
	mov	dps, #0x01
	inc	dptr
	movx	a,@dptr
	mov	dps, #0x00
;	genCmp #2
;	genCmp #4
;	genCmp #4.1
	xch	a, b
	inc	dptr
	movx	a,@dptr
	xch	a, b
	subb	a,b
;	genCmp #1: 0/0/3
	mov	dps, #0x01
	inc	dptr
	movx	a,@dptr
	mov	dps, #0x00
;	genCmp #2
;	genCmp #4
;	genCmp #4.1
	xch	a, b
	inc	dptr
	movx	a,@dptr
	xch	a, b
	subb	a,b
;	genIfxJump 
	jnc	00119$
	ljmp	00106$
00119$:
;	_divulong.c 42
;	genMinus 
	mov	dptr,#__divulong_reste_1_1
	mov	dps, #0x01
	mov	dptr, #__divulong_PARM_2
	dec	dps
	clr	c
	movx	a,@dptr
	xch	a, ap
	inc	dps
	movx	a,@dptr
	xch	a, ap
	subb	a,ap
	push	acc
	dec	dps
	inc	dptr
	movx	a,@dptr
	xch	a, ap
	inc	dps
	inc	dptr
	movx	a,@dptr
	xch	a, ap
	subb	a,ap
	push	acc
	dec	dps
	inc	dptr
	movx	a,@dptr
	xch	a, ap
	inc	dps
	inc	dptr
	movx	a,@dptr
	xch	a, ap
	subb	a,ap
	push	acc
	dec	dps
	inc	dptr
	movx	a,@dptr
	xch	a, ap
	inc	dps
	inc	dptr
	movx	a,@dptr
	xch	a, ap
	subb	a,ap
	push	acc
	mov	dps, #0x00
	pop	acc
	mov	r1,a
	pop	acc
	mov	r0,a
	pop	acc
	mov	r7,a
	pop	acc
;	genAssign 
;	genAssign: resultIsFar = TRUE
; Peephole 100   removed redundant mov
	mov  r6,a
	mov  dptr,#__divulong_reste_1_1
	movx @dptr,a
	inc	dptr
	mov	a,r7
	movx	@dptr,a
	inc	dptr
	mov	a,r0
	movx	@dptr,a
	inc	dptr
	mov	a,r1
	movx	@dptr,a
;	_divulong.c 44
;	genOr 
	orl	ar2,#0x01
;	genLabel 
00106$:
;	_divulong.c 46
;	genDjnz
	mov	dptr,#__divulong_count_1_1
	movx	a,@dptr
	dec	a
	movx	@dptr,a
; Peephole 162   removed sjmp by inverse jump logic
	jz   00121$
00120$:
	ljmp	00105$
00121$:
;	_divulong.c 48
;	genRet 
	mov	dpl,r2
	mov	dph,r3
	mov	dpx,r4
	mov	b,r5
;	genLabel 
00108$:
;	genEndFunction 
	ret
	.area CSEG    (CODE)