_fsadd.asm

很少见的源码公开的msc51和z80的c编译器。

;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.3.0 Thu Sep 20 10:57:12 2001

;--------------------------------------------------------
	.module _fsadd
	
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl ___fsadd_PARM_2
	.globl ___fsadd
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; special function bits 
;--------------------------------------------------------
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
___fsadd_PARM_2::
	.ds 4
___fsadd_mant1_1_1::
	.ds 4
___fsadd_mant2_1_1::
	.ds 4
___fsadd_fl1_1_1::
	.ds 4
___fsadd_fl2_1_1::
	.ds 4
___fsadd_exp1_1_1::
	.ds 2
___fsadd_exp2_1_1::
	.ds 2
___fsadd_sign_1_1::
	.ds 4
;--------------------------------------------------------
; overlayable items in internal ram 
;--------------------------------------------------------
	.area OSEG    (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
	.area ISEG    (DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
	.area BSEG    (BIT)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
	.area XSEG    (XDATA)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME	 (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function '__fsadd'
;------------------------------------------------------------
;a2                        Allocated to in memory with name '___fsadd_PARM_2'
;a1                        Allocated to registers r2 r3 r4 r5 
;mant1                     Allocated to in memory with name '___fsadd_mant1_1_1'
;mant2                     Allocated to in memory with name '___fsadd_mant2_1_1'
;fl1                       Allocated to in memory with name '___fsadd_fl1_1_1'
;fl2                       Allocated to in memory with name '___fsadd_fl2_1_1'
;exp1                      Allocated to in memory with name '___fsadd_exp1_1_1'
;exp2                      Allocated to in memory with name '___fsadd_exp2_1_1'
;sign                      Allocated to in memory with name '___fsadd_sign_1_1'
;	_fsadd.c 17
;	-----------------------------------------
;	 function __fsadd
;	-----------------------------------------
___fsadd:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
;	_fsadd.c 101
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;	_fsadd.c 22
	clr	a
	mov	(___fsadd_sign_1_1 + 3),a
	mov	(___fsadd_sign_1_1 + 2),a
	mov	(___fsadd_sign_1_1 + 1),a
	mov	___fsadd_sign_1_1,a
;	_fsadd.c 24
	mov	___fsadd_fl1_1_1,r2
	mov	(___fsadd_fl1_1_1 + 1),r3
	mov	(___fsadd_fl1_1_1 + 2),r4
	mov	(___fsadd_fl1_1_1 + 3),r5
;	_fsadd.c 25
	mov	___fsadd_fl2_1_1,___fsadd_PARM_2
	mov	(___fsadd_fl2_1_1 + 1),(___fsadd_PARM_2 + 1)
	mov	(___fsadd_fl2_1_1 + 2),(___fsadd_PARM_2 + 2)
	mov	(___fsadd_fl2_1_1 + 3),(___fsadd_PARM_2 + 3)
;	_fsadd.c 28
	mov	a,___fsadd_fl1_1_1
	orl	a,(___fsadd_fl1_1_1 + 1)
	orl	a,(___fsadd_fl1_1_1 + 2)
	orl	a,(___fsadd_fl1_1_1 + 3)
; Peephole 109   removed ljmp by inverse jump logic
	jnz  00102$
00146$:
;	_fsadd.c 29
	mov	dpl,___fsadd_fl2_1_1
	mov	dph,(___fsadd_fl2_1_1 + 1)
	mov	b,(___fsadd_fl2_1_1 + 2)
	mov	a,(___fsadd_fl2_1_1 + 3)
	ljmp	00128$
00102$:
;	_fsadd.c 30
	mov	a,___fsadd_fl2_1_1
	orl	a,(___fsadd_fl2_1_1 + 1)
	orl	a,(___fsadd_fl2_1_1 + 2)
	orl	a,(___fsadd_fl2_1_1 + 3)
; Peephole 109   removed ljmp by inverse jump logic
	jnz  00104$
00147$:
;	_fsadd.c 31
	mov	dpl,___fsadd_fl1_1_1
	mov	dph,(___fsadd_fl1_1_1 + 1)
	mov	b,(___fsadd_fl1_1_1 + 2)
	mov	a,(___fsadd_fl1_1_1 + 3)
	ljmp	00128$
00104$:
;	_fsadd.c 33
	mov	r2,(___fsadd_fl1_1_1 + 2)
	mov	a,(___fsadd_fl1_1_1 + 3)
	mov	c,acc.7
	xch	a,r2
	rlc	a
	xch	a,r2
	rlc	a
	xch	a,r2
	anl	a,#0x01
	mov	r3,a
	mov	r4,#0x00
	mov	r5,#0x00
	mov	r3,#0x00
	mov	r4,#0x00
	mov	r5,#0x00
	mov	___fsadd_exp1_1_1,r2
	mov	(___fsadd_exp1_1_1 + 1),r3
;	_fsadd.c 34
	mov	r2,(___fsadd_fl2_1_1 + 2)
	mov	a,(___fsadd_fl2_1_1 + 3)
	mov	c,acc.7
	xch	a,r2
	rlc	a
	xch	a,r2
	rlc	a
	xch	a,r2
	anl	a,#0x01
	mov	r3,a
	mov	r4,#0x00
	mov	r5,#0x00
	mov	r3,#0x00
	mov	r4,#0x00
	mov	r5,#0x00
	mov	___fsadd_exp2_1_1,r2
	mov	(___fsadd_exp2_1_1 + 1),r3
;	_fsadd.c 36
	mov	a,#0x19
	add	a,___fsadd_exp2_1_1
	mov	r2,a
; Peephole 180   changed mov to clr
	clr  a
	addc	a,(___fsadd_exp2_1_1 + 1)
	mov	r3,a
	clr	c
	mov	a,r2
	subb	a,___fsadd_exp1_1_1
	mov	a,r3
	xrl	a,#0x80
	mov	b,(___fsadd_exp1_1_1 + 1)
	xrl	b,#0x80
	subb	a,b
; Peephole 108   removed ljmp by inverse jump logic
	jnc  00106$
00148$:
;	_fsadd.c 37
	mov	dpl,___fsadd_fl1_1_1
	mov	dph,(___fsadd_fl1_1_1 + 1)
	mov	b,(___fsadd_fl1_1_1 + 2)
	mov	a,(___fsadd_fl1_1_1 + 3)
	lcall	___slong2fs
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
; Peephole 191   removed redundant mov
	mov  r5,a
	mov  dpl,r2
	mov  dph,r3
	mov  b,r4
	ljmp	00128$
00106$:
;	_fsadd.c 38
	mov	a,#0x19
	add	a,___fsadd_exp1_1_1
	mov	r2,a
; Peephole 180   changed mov to clr
	clr  a
	addc	a,(___fsadd_exp1_1_1 + 1)
	mov	r3,a
	clr	c
	mov	a,r2
	subb	a,___fsadd_exp2_1_1
	mov	a,r3
	xrl	a,#0x80
	mov	b,(___fsadd_exp2_1_1 + 1)
	xrl	b,#0x80
	subb	a,b
; Peephole 108   removed ljmp by inverse jump logic
	jnc  00108$
00149$:
;	_fsadd.c 39
	mov	dpl,___fsadd_fl2_1_1
	mov	dph,(___fsadd_fl2_1_1 + 1)
	mov	b,(___fsadd_fl2_1_1 + 2)
	mov	a,(___fsadd_fl2_1_1 + 3)
	lcall	___slong2fs
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
; Peephole 191   removed redundant mov
	mov  r5,a
	mov  dpl,r2
	mov  dph,r3
	mov  b,r4
	ljmp	00128$
00108$:
;	_fsadd.c 42
	mov	r2,___fsadd_fl1_1_1
	mov	r3,(___fsadd_fl1_1_1 + 1)
	mov	r4,(___fsadd_fl1_1_1 + 2)
	mov	r5,(___fsadd_fl1_1_1 + 3)
	anl	ar4,#0x7F
	mov	r5,#0x00
	orl	ar4,#0x80
	mov	(___fsadd_mant1_1_1 + 2),r4
	mov	a,r5
	anl	a,#0x03
	mov	c,acc.0
	xch	a,(___fsadd_mant1_1_1 + 2)
	rrc	a
	xch	a,(___fsadd_mant1_1_1 + 2)
	rrc	a
	mov	c,acc.0
	xch	a,(___fsadd_mant1_1_1 + 2)
	rrc	a
	xch	a,(___fsadd_mant1_1_1 + 2)
	rrc	a
	xch	a,(___fsadd_mant1_1_1 + 2)
	mov	(___fsadd_mant1_1_1 + 3),a
	mov	a,r3
	rr	a
	rr	a
	anl	a,#0x3f
	orl	a,(___fsadd_mant1_1_1 + 2)
	mov	(___fsadd_mant1_1_1 + 2),a
	mov	___fsadd_mant1_1_1,r2
	mov	a,r3
	anl	a,#0x03
	mov	c,acc.0
	xch	a,___fsadd_mant1_1_1
	rrc	a
	xch	a,___fsadd_mant1_1_1
	rrc	a
	mov	c,acc.0
	xch	a,___fsadd_mant1_1_1
	rrc	a
	xch	a,___fsadd_mant1_1_1
	rrc	a
	xch	a,___fsadd_mant1_1_1
	mov	(___fsadd_mant1_1_1 + 1),a
;	_fsadd.c 43
	mov	r2,___fsadd_fl2_1_1
	mov	r3,(___fsadd_fl2_1_1 + 1)
	mov	r4,(___fsadd_fl2_1_1 + 2)
	mov	r5,(___fsadd_fl2_1_1 + 3)
	anl	ar4,#0x7F
	mov	r5,#0x00
	orl	ar4,#0x80
	mov	(___fsadd_mant2_1_1 + 2),r4
	mov	a,r5
	anl	a,#0x03
	mov	c,acc.0
	xch	a,(___fsadd_mant2_1_1 + 2)
	rrc	a
	xch	a,(___fsadd_mant2_1_1 + 2)
	rrc	a
	mov	c,acc.0
	xch	a,(___fsadd_mant2_1_1 + 2)
	rrc	a
	xch	a,(___fsadd_mant2_1_1 + 2)
	rrc	a
	xch	a,(___fsadd_mant2_1_1 + 2)
	mov	(___fsadd_mant2_1_1 + 3),a
	mov	a,r3
	rr	a
	rr	a
	anl	a,#0x3f
	orl	a,(___fsadd_mant2_1_1 + 2)
	mov	(___fsadd_mant2_1_1 + 2),a
	mov	___fsadd_mant2_1_1,r2
	mov	a,r3
	anl	a,#0x03
	mov	c,acc.0
	xch	a,___fsadd_mant2_1_1
	rrc	a
	xch	a,___fsadd_mant2_1_1
	rrc	a
	mov	c,acc.0
	xch	a,___fsadd_mant2_1_1
	rrc	a
	xch	a,___fsadd_mant2_1_1
	rrc	a
	xch	a,___fsadd_mant2_1_1
	mov	(___fsadd_mant2_1_1 + 1),a
;	_fsadd.c 45
	mov	a,(___fsadd_fl1_1_1 + 3)
	rl	a
	anl	a,#0x01
; Peephole 105   removed redundant mov
	mov  r2,a
; Peephole 110   removed ljmp by inverse jump logic
	jz  00110$
00150$:
;	_fsadd.c 46
	clr	c
	clr	a
	subb	a,___fsadd_mant1_1_1
	mov	___fsadd_mant1_1_1,a
	clr	a
	subb	a,(___fsadd_mant1_1_1 + 1)
	mov	(___fsadd_mant1_1_1 + 1),a
	clr	a
	subb	a,(___fsadd_mant1_1_1 + 2)
	mov	(___fsadd_mant1_1_1 + 2),a
	clr	a
	subb	a,(___fsadd_mant1_1_1 + 3)
	mov	(___fsadd_mant1_1_1 + 3),a
00110$:
;	_fsadd.c 47
	mov	a,(___fsadd_fl2_1_1 + 3)
	rl	a
	anl	a,#0x01
; Peephole 105   removed redundant mov
	mov  r2,a
; Peephole 110   removed ljmp by inverse jump logic
	jz  00112$
00151$:
;	_fsadd.c 48
	clr	c
	clr	a
	subb	a,___fsadd_mant2_1_1
	mov	___fsadd_mant2_1_1,a
	clr	a