_fsmul.asm

很少见的源码公开的msc51和z80的c编译器。

;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.3.0 Thu Sep 20 10:57:13 2001

;--------------------------------------------------------
	.module _fsmul
	
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl ___fsmul_PARM_2
	.globl ___fsmul
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; special function bits 
;--------------------------------------------------------
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
___fsmul_PARM_2::
	.ds 4
___fsmul_fl1_1_1::
	.ds 4
___fsmul_fl2_1_1::
	.ds 4
___fsmul_result_1_1::
	.ds 4
___fsmul_exp_1_1::
	.ds 2
___fsmul_sloc0_1_0::
	.ds 4
;--------------------------------------------------------
; overlayable items in internal ram 
;--------------------------------------------------------
	.area OSEG    (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
	.area ISEG    (DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
	.area BSEG    (BIT)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
	.area XSEG    (XDATA)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME	 (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function '__fsmul'
;------------------------------------------------------------
;a2                        Allocated to in memory with name '___fsmul_PARM_2'
;a1                        Allocated to registers r2 r3 r4 r5 
;fl1                       Allocated to in memory with name '___fsmul_fl1_1_1'
;fl2                       Allocated to in memory with name '___fsmul_fl2_1_1'
;result                    Allocated to in memory with name '___fsmul_result_1_1'
;exp                       Allocated to in memory with name '___fsmul_exp_1_1'
;sign                      Allocated to registers r2 
;sloc0                     Allocated to in memory with name '___fsmul_sloc0_1_0'
;	_fsmul.c 81
;	-----------------------------------------
;	 function __fsmul
;	-----------------------------------------
___fsmul:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
;	_fsmul.c 125
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r5,a
;	_fsmul.c 88
	mov	___fsmul_fl1_1_1,r2
	mov	(___fsmul_fl1_1_1 + 1),r3
	mov	(___fsmul_fl1_1_1 + 2),r4
	mov	(___fsmul_fl1_1_1 + 3),r5
;	_fsmul.c 89
	mov	___fsmul_fl2_1_1,___fsmul_PARM_2
	mov	(___fsmul_fl2_1_1 + 1),(___fsmul_PARM_2 + 1)
	mov	(___fsmul_fl2_1_1 + 2),(___fsmul_PARM_2 + 2)
	mov	(___fsmul_fl2_1_1 + 3),(___fsmul_PARM_2 + 3)
;	_fsmul.c 91
	mov	a,___fsmul_fl1_1_1
	orl	a,(___fsmul_fl1_1_1 + 1)
	orl	a,(___fsmul_fl1_1_1 + 2)
	orl	a,(___fsmul_fl1_1_1 + 3)
; Peephole 110   removed ljmp by inverse jump logic
	jz  00101$
00114$:
	mov	a,___fsmul_fl2_1_1
	orl	a,(___fsmul_fl2_1_1 + 1)
	orl	a,(___fsmul_fl2_1_1 + 2)
	orl	a,(___fsmul_fl2_1_1 + 3)
; Peephole 109   removed ljmp by inverse jump logic
	jnz  00102$
00115$:
00101$:
;	_fsmul.c 92
; Peephole 3.a   changed mov to clr
; Peephole 3.b   changed mov to clr
; Peephole 3.b   changed mov to clr
	clr  a
	mov  dpl,a
	mov  dph,a
	mov  b,a
	ljmp	00107$
00102$:
;	_fsmul.c 95
	mov	a,(___fsmul_fl1_1_1 + 3)
	rl	a
	anl	a,#0x01
	mov	r2,a
	mov	a,(___fsmul_fl2_1_1 + 3)
	rl	a
	anl	a,#0x01
; Peephole 105   removed redundant mov
	mov  r3,a
	xrl	ar2,a
;	_fsmul.c 96
	mov	r3,(___fsmul_fl1_1_1 + 2)
	mov	a,(___fsmul_fl1_1_1 + 3)
	mov	c,acc.7
	xch	a,r3
	rlc	a
	xch	a,r3
	rlc	a
	xch	a,r3
	anl	a,#0x01
	mov	r4,a
; Peephole 3.c   changed mov to clr
; Peephole 3.b   changed mov to clr
; Peephole 3.b   changed mov to clr
; Peephole 3.b   changed mov to clr
	clr  a
	mov  r5,a
	mov  r6,a
	mov  r4,a
	mov  r5,a
	mov  r6,a
	mov  a,r3
	add	a,#0x82
	mov	r3,a
	mov	a,r4
	addc	a,#0xff
	mov	r4,a
	mov	a,r5
	addc	a,#0xff
	mov	r5,a
	mov	a,r6
	addc	a,#0xff
	mov	r6,a
	mov	___fsmul_exp_1_1,r3
	mov	(___fsmul_exp_1_1 + 1),r4
;	_fsmul.c 97
	mov	r3,(___fsmul_fl2_1_1 + 2)
	mov	a,(___fsmul_fl2_1_1 + 3)
	mov	c,acc.7
	xch	a,r3
	rlc	a
	xch	a,r3
	rlc	a
	xch	a,r3
	anl	a,#0x01
	mov	r4,a
	mov	r5,#0x00
	mov	r6,#0x00
	mov	r4,#0x00
	mov	r5,#0x00
	mov	r6,#0x00
	mov	___fsmul_sloc0_1_0,___fsmul_exp_1_1
	mov	(___fsmul_sloc0_1_0 + 1),(___fsmul_exp_1_1 + 1)
	mov	a,(___fsmul_exp_1_1 + 1)
	rlc	a
	subb	a,acc
	mov	(___fsmul_sloc0_1_0 + 2),a
	mov	(___fsmul_sloc0_1_0 + 3),a
	mov	a,r3
	add	a,___fsmul_sloc0_1_0
	mov	r3,a
	mov	a,r4
	addc	a,(___fsmul_sloc0_1_0 + 1)
	mov	r4,a
	mov	a,r5
	addc	a,(___fsmul_sloc0_1_0 + 2)
	mov	r5,a
	mov	a,r6
	addc	a,(___fsmul_sloc0_1_0 + 3)
	mov	r6,a
	mov	___fsmul_exp_1_1,r3
	mov	(___fsmul_exp_1_1 + 1),r4
;	_fsmul.c 99
	mov	r3,___fsmul_fl1_1_1
	mov	r4,(___fsmul_fl1_1_1 + 1)
	mov	r5,(___fsmul_fl1_1_1 + 2)
	mov	r6,(___fsmul_fl1_1_1 + 3)
	anl	ar5,#0x7F
	mov	r6,#0x00
	orl	ar5,#0x80
	mov	___fsmul_fl1_1_1,r3
	mov	(___fsmul_fl1_1_1 + 1),r4
	mov	(___fsmul_fl1_1_1 + 2),r5
	mov	(___fsmul_fl1_1_1 + 3),r6
;	_fsmul.c 100
	mov	r3,___fsmul_fl2_1_1
	mov	r4,(___fsmul_fl2_1_1 + 1)
	mov	r5,(___fsmul_fl2_1_1 + 2)
	mov	r6,(___fsmul_fl2_1_1 + 3)
	anl	ar5,#0x7F
	mov	r6,#0x00
	orl	ar5,#0x80
	mov	___fsmul_fl2_1_1,r3
	mov	(___fsmul_fl2_1_1 + 1),r4
	mov	(___fsmul_fl2_1_1 + 2),r5
	mov	(___fsmul_fl2_1_1 + 3),r6
;	_fsmul.c 103
	mov	r3,(___fsmul_fl1_1_1 + 1)
	mov	r4,(___fsmul_fl1_1_1 + 2)
	mov	a,(___fsmul_fl1_1_1 + 3)
	mov	r5,a
	rlc	a
	subb	a,acc
	mov	r6,a
	mov	__mulslong_PARM_2,(___fsmul_fl2_1_1 + 1)
	mov	(__mulslong_PARM_2 + 1),(___fsmul_fl2_1_1 + 2)
	mov	a,(___fsmul_fl2_1_1 + 3)
	mov	(__mulslong_PARM_2 + 2),a
	rlc	a
	subb	a,acc
	mov	(__mulslong_PARM_2 + 3),a
	mov	dpl,r3
	mov	dph,r4
	mov	b,r5
	mov	a,r6
	push	ar2
	lcall	__mulslong
	mov	r3,dpl
	mov	r4,dph
	mov	r5,b
	mov	r6,a
	pop	ar2
	mov	___fsmul_result_1_1,r3
	mov	(___fsmul_result_1_1 + 1),r4
	mov	(___fsmul_result_1_1 + 2),r5
	mov	(___fsmul_result_1_1 + 3),r6
;	_fsmul.c 104
	mov	r3,___fsmul_fl1_1_1
	mov	r4,(___fsmul_fl1_1_1 + 1)
	mov	r5,(___fsmul_fl1_1_1 + 2)
	mov	r6,(___fsmul_fl1_1_1 + 3)
	mov	r4,#0x00
	mov	r5,#0x00
	mov	r6,#0x00
	mov	__mululong_PARM_2,(___fsmul_fl2_1_1 + 1)
	mov	(__mululong_PARM_2 + 1),(___fsmul_fl2_1_1 + 2)
	mov	(__mululong_PARM_2 + 2),(___fsmul_fl2_1_1 + 3)
	mov	(__mululong_PARM_2 + 3),#0x00
	mov	dpl,r3
	mov	dph,r4
	mov	b,r5
	mov	a,r6
	push	ar2
	lcall	__mululong
	mov	r3,dpl
	mov	r4,dph
	mov	r5,b
	mov	r6,a
	pop	ar2
	mov	ar3,r4
	mov	ar4,r5
	mov	ar5,r6
	mov	r6,#0x00
	mov	a,r3
	add	a,___fsmul_result_1_1
	mov	___fsmul_result_1_1,a
	mov	a,r4
	addc	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
	mov	a,r5
	addc	a,(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),a
	mov	a,r6
	addc	a,(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),a
;	_fsmul.c 105
	mov	r3,___fsmul_fl2_1_1
	mov	r4,(___fsmul_fl2_1_1 + 1)
	mov	r5,(___fsmul_fl2_1_1 + 2)
	mov	r6,(___fsmul_fl2_1_1 + 3)
	mov	r4,#0x00
	mov	r5,#0x00
	mov	r6,#0x00
	mov	__mululong_PARM_2,(___fsmul_fl1_1_1 + 1)
	mov	(__mululong_PARM_2 + 1),(___fsmul_fl1_1_1 + 2)
	mov	(__mululong_PARM_2 + 2),(___fsmul_fl1_1_1 + 3)
	mov	(__mululong_PARM_2 + 3),#0x00
	mov	dpl,r3
	mov	dph,r4
	mov	b,r5
	mov	a,r6
	push	ar2
	lcall	__mululong
	mov	r3,dpl
	mov	r4,dph
	mov	r5,b
	mov	r6,a
	pop	ar2
	mov	ar3,r4
	mov	ar4,r5
	mov	ar5,r6
	mov	r6,#0x00
	mov	a,r3
	add	a,___fsmul_result_1_1
	mov	___fsmul_result_1_1,a
	mov	a,r4
	addc	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
	mov	a,r5
	addc	a,(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),a
	mov	a,r6
	addc	a,(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),a
;	_fsmul.c 107
	mov	a,(___fsmul_result_1_1 + 3)
; Peephole 111   removed ljmp by inverse jump logic
	jnb  acc.7,00105$
00116$:
;	_fsmul.c 110
	mov	a,#0x80
	add	a,___fsmul_result_1_1
	mov	___fsmul_result_1_1,a
; Peephole 180   changed mov to clr
	clr  a
	addc	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
; Peephole 180   changed mov to clr
	clr  a
	addc	a,(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),a
; Peephole 180   changed mov to clr
	clr  a
	addc	a,(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),a
;	_fsmul.c 111
	mov	___fsmul_result_1_1,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),#0x00
; Peephole 132   changed ljmp to sjmp
	sjmp 00106$
00105$:
;	_fsmul.c 116
	mov	a,#0x40
	add	a,___fsmul_result_1_1
	mov	___fsmul_result_1_1,a
; Peephole 180   changed mov to clr
	clr  a
	addc	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
; Peephole 180   changed mov to clr
	clr  a
	addc	a,(___fsmul_result_1_1 + 2)
	mov	(___fsmul_result_1_1 + 2),a
; Peephole 180   changed mov to clr
	clr  a
	addc	a,(___fsmul_result_1_1 + 3)
	mov	(___fsmul_result_1_1 + 3),a
;	_fsmul.c 117
	mov	a,(___fsmul_result_1_1 + 1)
	mov	c,acc.7
	xch	a,___fsmul_result_1_1
	rlc	a
	xch	a,___fsmul_result_1_1
	rlc	a
	xch	a,___fsmul_result_1_1
	anl	a,#0x01
	mov	(___fsmul_result_1_1 + 1),a
	mov	a,(___fsmul_result_1_1 + 2)
	add	a,acc
	orl	a,(___fsmul_result_1_1 + 1)
	mov	(___fsmul_result_1_1 + 1),a
	mov	a,(___fsmul_result_1_1 + 3)
	mov	c,acc.7
	xch	a,(___fsmul_result_1_1 + 2)
	rlc	a
	xch	a,(___fsmul_result_1_1 + 2)
	rlc	a
	xch	a,(___fsmul_result_1_1 + 2)
	anl	a,#0x01
	mov	(___fsmul_result_1_1 + 3),a
;	_fsmul.c 118
	dec	___fsmul_exp_1_1
	mov	a,#0xff
	cjne	a,___fsmul_exp_1_1,00117$
	dec	(___fsmul_exp_1_1 + 1)
00117$:
00106$:
;	_fsmul.c 121
	anl	(___fsmul_result_1_1 + 2),#0x7F
;	_fsmul.c 124
	mov	r0,#___fsmul_fl1_1_1
	mov	a,r2
; Peephole 110   removed ljmp by inverse jump logic
	jz  00109$
00118$:
	mov	r2,#0x00
	mov	r3,#0x00
	mov	r4,#0x00
	mov	r5,#0x80
; Peephole 132   changed ljmp to sjmp
	sjmp 00110$
00109$:
	mov	r2,#0x00
	mov	r3,#0x00
	mov	r4,#0x00
	mov	r5,#0x00
00110$:
	mov	___fsmul_sloc0_1_0,___fsmul_exp_1_1
	mov	(___fsmul_sloc0_1_0 + 1),(___fsmul_exp_1_1 + 1)
	mov	a,(___fsmul_exp_1_1 + 1)
	rlc	a
	subb	a,acc
	mov	(___fsmul_sloc0_1_0 + 2),a
	mov	(___fsmul_sloc0_1_0 + 3),a
	mov	(___fsmul_sloc0_1_0 + 2),___fsmul_sloc0_1_0
	mov	a,(___fsmul_sloc0_1_0 + 1)
	anl	a,#0x01
	mov	c,acc.0
	xch	a,(___fsmul_sloc0_1_0 + 2)
	rrc	a
	xch	a,(___fsmul_sloc0_1_0 + 2)
	rrc	a
	xch	a,(___fsmul_sloc0_1_0 + 2)
	mov	(___fsmul_sloc0_1_0 + 3),a
	mov	(___fsmul_sloc0_1_0 + 1),#0x00
	mov	___fsmul_sloc0_1_0,#0x00
	mov	a,___fsmul_sloc0_1_0
	orl	ar2,a
	mov	a,(___fsmul_sloc0_1_0 + 1)
	orl	ar3,a
	mov	a,(___fsmul_sloc0_1_0 + 2)
	orl	ar4,a
	mov	a,(___fsmul_sloc0_1_0 + 3)
	orl	ar5,a
	mov	a,___fsmul_result_1_1
	orl	ar2,a
	mov	a,(___fsmul_result_1_1 + 1)
	orl	ar3,a
	mov	a,(___fsmul_result_1_1 + 2)
	orl	ar4,a
	mov	a,(___fsmul_result_1_1 + 3)
	orl	ar5,a
	mov	@r0,ar2
	inc	r0
	mov	@r0,ar3
	inc	r0
	mov	@r0,ar4
	inc	r0
	mov	@r0,ar5
;	_fsmul.c 125
	mov	dpl,___fsmul_fl1_1_1
	mov	dph,(___fsmul_fl1_1_1 + 1)
	mov	b,(___fsmul_fl1_1_1 + 2)
	mov	a,(___fsmul_fl1_1_1 + 3)
00107$:
	ret
	.area CSEG    (CODE)