📄 复件 uart.c
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Flag_Reader_Timeout = 1;
}
*/
//****************************************************************************
//readerOpen()----Open and config uart2 ;
// Enable uart2 interrupt(Tx,Rx)
//
//
//****************************************************************************
int readerOpen( int BaudRate, int DataBits, int StopBits, int Parity, int EvenParity )
{
unsigned long * volatile pulPtr = (unsigned long *)HwBaseAddress;
long lRates[12] = { 115200, 76800, 57600, 38400, 28800, 19200, 14400, 9600,
4800, 2400, 1200, 110 };
long lDivisors[12] = { 1, 2, 3, 5, 7, 11, 15, 23, 47, 95, 191, 2094 };
long lIdx, lConfig;
void (*dummy)(int);
STATUS status;
//OPENED?
if( lPort2Enabled )
return( OPENED );
//Create UART2Rx timer 200ms 2002-5-14 11:10
// status=NU_Create_Timer(&UART2RxTimer_Control,"UART2RxTimer",UART2RxTimer,1,20,0,NU_DISABLE_TIMER);
status=NU_Create_HISR(&UART2Tx_HISR_Control, "UART2Tx_HISR",UART2Tx_HISR,2,UART2Tx_HISR_Stack,2000);
//
status=NU_Create_HISR(&UART2Rx_HISR_Control, "UART2Rx_HISR",UART2Rx_HISR,2,UART2Rx_HISR_Stack,2000);
NU_Register_LISR( LISR_UART2_TX, UART2_LISR, &dummy );
NU_Register_LISR( LISR_UART2_RX, UART2_LISR, &dummy );
//
// Check for a valid data rate.
//
for(lIdx = 0; lIdx < 12; lIdx++)
{
if(lRates[lIdx] == BaudRate)
{
lConfig = lDivisors[lIdx];
break;
}
}
if(lIdx == 12)
return( FAIL );
//
// Check for a valid number of data bits.
//
switch(DataBits)
{
case 5:
lConfig |= HwUartControlDataLength5;
break;
case 6:
lConfig |= HwUartControlDataLength6;
break;
case 7:
lConfig |= HwUartControlDataLength7;
break;
case 8:
lConfig |= HwUartControlDataLength8;
break;
default:
return( FAIL );
}
//
// Check for a valid number of stop bits.
//
if(StopBits == 2)
lConfig |= HwUartControlTwoStopBits;
else if(StopBits != 1)
return( FAIL );
// Set the parity as specified.
//
if(Parity)
{
//
// Parity was requested, so enable parity.
//
lConfig |= HwUartControlParityEnable;
//
// See if even parity was requested.
//
if(EvenParity)
//
// Change the parity to even (the default is odd).
//
lConfig |= HwUartControlParityEven;
}
// Configure UART2.
//
pulPtr[HwUart2Control >> 2] = lConfig | HwUartControlFifoEnable;
//2002-5-14 15:55
// Clear the local FIFO buffers.
//
//iPort2TxRead = iPort2TxWrite = 0;
//Added 2002-5-14 15:55
readerClear();
// Mark UART2 as being configured.
//
lPort2Enabled = 1;
// Turn on UART2. //enable uart2 interrupt
//
pulPtr[HwControl2 >> 2] |= HwControlUartEnable;
//Disable SS2RXEN and SS2TXEN for test down
pulPtr[HwControl2 >> 2] &= 0xFF6F;
// Unmask the UART2 receive interrupt.
//
//pulPtr[HwIntMask2 >> 2] |= HwIrqUartRx; //the same as
irq_enable(LISR_UART2_RX);
return SUCCEED ;
}
//****************************************************************************
//readerClose()----Close uart2 ;
// Disable uart2 interrupt(Tx,Rx)
// clear Rx Tx buffer and reset read/write pointer
//
//
//****************************************************************************
int readerClose( void )
{
unsigned long * volatile pulPtr = (unsigned long *)HwBaseAddress;
int i;
/* 2002-5-14 15:57
for(i=0;i< SIZE;i++)
{
pcPort2TxData[i] = Rxbuffer[i] = 0x00;
Command_Buf2[i] = Command_Buf3[i]=0x00;
}
iPort2TxRead = iPort2TxWrite = 0;
pr=pw=0;
Rxlen=cstart=0;
// Mask the UART2 interrupts.
//
*/
//Added 2002-5-14 15:54
readerClear();
//
irq_disable(LISR_UART2_TX);
irq_disable(LISR_UART2_RX);
//
// Turn off UART2.
//
pulPtr[HwControl2 >> 2] &= ~HwControlUartEnable;
//
// Mark UART2 as not being configured.
//
lPort2Enabled = 0;
//2002-5-15 8:15
//NU_Control_Timer(&UART2RxTimer_Control,NU_DISABLE_TIMER);
//Delete UART2 HISR;
NU_Delete_HISR(&UART2Tx_HISR_Control);
NU_Delete_HISR(&UART2Rx_HISR_Control);
//delete the timer 2002-5-14 11:12
//NU_Delete_Timer(&UART2RxTimer_Control);
return SUCCEED ;
}
//****************************************************************************
//readerRead()----Read one complete command or response from reader
//
// return: success ----return command/respose length
// fail--------return NO_CONTENT
//
//****************************************************************************
int readerRead( unsigned char * response )
{
unsigned int Rec_Len = 0, i;
// UART2 is not opened
if ( !lPort2Enabled )
return NOT_OPENED;
/* //Remove receive timer 2002-5-14 11:17
if((Flag_Reader_Timeout)&&(actual_commnum <=0 ) )
{
Flag_Reader_Timeout=0;
actual_commnum=0;
return FAIL;
}
else
{
*/
if( actual_commnum )
{
//To be sure get the actual command length
if( (pr+2) < SIZE)
{
Rec_Len=(unsigned int)Command_Buf3[pr+2]+3;
}
else
{
Rec_Len=(unsigned int)Command_Buf3[2-(SIZE-pr)]+3 ;
}
for(i=0;i<Rec_Len;i++)
{
if(pr>=SIZE)
pr=0;
*( response + i ) = Command_Buf3[pr++];
}
actual_commnum--;
return Rec_Len;
}
else
{
return NO_CONTENT ;
}
// }
}
//****************************************************************************
//readerWrite()----Write card command to uart2tx buffer
//
//
//****************************************************************************
int readerWrite( unsigned char * command, int command_Len )
{
int i;
//unsigned long * volatile pulPtr = (unsigned long *)HwBaseAddress;
//
// UART2 is not opened
//
if ( !lPort2Enabled )
return NOT_OPENED;
// send chars
//
for(i=0;i<command_Len;i++)
{
if( iPort2TxWrite>=SIZE )
iPort2TxWrite=0x0;
pcPort2TxData[iPort2TxWrite++] = *( command+i );
}
// Enable the transmit interrupt for UART2.
// pulPtr[HwIntMask2 >> 2] |= HwIrqUartTx;
irq_enable(LISR_UART2_TX);
return SUCCEED;
}
//****************************************************************************
//readerClear()----Reset uart2 ;
// clear Rx Tx buffer and reset read/write pointer
//
//
//****************************************************************************
int readerClear( void )
{
unsigned long * volatile pulPtr = (unsigned long *)HwBaseAddress;
int i;
for(i=0;i< SIZE;i++)
{
pcPort2TxData[i] = Rxbuffer[i] = 0x00;
Command_Buf2[i] = Command_Buf3[i]=0x00;
}
iPort2TxRead = iPort2TxWrite = 0;
pr=pw=0;
Rxlen=cstart=0;
}
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