bsestart.s

ppc860的ucos part

	ori		r12, r12, CS_BR0_INIT@l 
	stw		r12, CS_BR0(r4)

	# program OR0 
	lis		r9, CS_OR0_INIT@h
	ori		r9, r9, CS_OR0_INIT@l 
	stw		r9, CS_OR0(r4)

	# Map CS1 to BCSR's

	# program BR1 
	lis		r12, CS_BR1_INIT@h
	ori		r12, r12, CS_BR1_INIT@l 
	stw		r12, CS_BR1(r4)

	# program OR1 
	lis		r9, CS_OR1_INIT@h
	ori		r9, r9, CS_OR1_INIT@l 
	stw		r9, CS_OR1(r4)

#################can't program DRAM while running out of DRAM
	.if 0		#can't program DRAM while running out of DRAM
	# ORx cannot be written without an exception while running out of 
		the memory being set up, thus this patch  
		when I get around to fixing it
	# Initialize UPMA (DRAM)
UpmaSetup:
	lis		r12, HI(UPMATableEnd)
	ori		r12, r12, LO(UPMATableEnd)
	bl		calc_reloc
	la		r9, 0(r12)

	lis		r12, HI(UPMATable)
	ori		r12, r12, LO(UPMATable)
	bl		calc_reloc

	sub		r9, r9, r12		# compute table size 
	srawi	r9, r9, 2		# in words 
	mtctr	r9				# set up counter  
	subi	r12, r12, 4		# set up pointer to table  

	# Command: OP=Write, UPMA, MAD=0, MB=CS1, MCLF=0 
	lis		r9, HI(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS1)
	ori		r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS1)

UpmaInit:	
	lwzu	r8, 4(r12)			# get data from table 
	stw		r8, MDR(0)(r4)		# store data to MD register 
	stw		r9, MCR(0)(r4)		# issue write command to MCR register 
	addi	r9, r9, 1			# update UPMA address in write command 
	bdnz	UpmaInit

dpram_patch:
	lis		r12, HI(patch_1)
	ori		r12, r12, LO(patch_1) 
	bl		calc_reloc

	lwz		r11, 0(r12)		# get store instruction 
	stw		r11, 0x2000(r4)		# store data to DPRAM 
	lwz		r11, 4(r12)		# get branch instruction 
	stw		r11, 0x2004(r4)		# store data to DPRAM 

	# Calculate the address of after_or0  
	lis		r12, HI(after_or2)		# load r12 with the address 
	ori		r12, r12, LO(after_or2)		# of after_or0 
	bl		calc_reloc
	mtspr	LR, r12			# save relocated return address into LR 
	la		r12, 0x2000(r4) # point to DPRAM  
	mtctr	r12
	bctr					# jump to DPRAM  

patch_1:
	stw		r9, OR0(0)(r4)	# store CS_OR0_INIT to CS0 option register  
	blr						# return to relocated address  

after_or2:

	# Map CS2 to DRAM

	# program BR2 
	lis		r12, CS_BR2_INIT@h
	ori		r12, r12, CS_BR2_INIT@l 
	stw		r12, CS_BR2(r4)

	# program OR2 
	lis		r9, CS_OR2_INIT@h
	ori		r9, r9, CS_OR2_INIT@l 
	stw		r9, CS_OR2(r4)

	.endif 		#can't program DRAM while running out of DRAM
#################can't program DRAM while running out of DRAM

	# Initialize UPMB (SDRAM) 
UPMBSetup:
	# Set up for 48 MHz clock commands
	lis		r12, UPMBTable_50End@ha
	ori		r12, r12, UPMBTable_50End@l
	la		r9, 0(r12)

	# Set up for 48 MHz clock commands
	lis		r12, UPMBTable_50@ha
	ori		r12, r12, UPMBTable_50@l
	la		r12, 0(r12)

	sub		r9, r9, r12		# compute table size 
	srawi	r9, r9, 2		# in words 
	mtctr	r9				# set up counter  
	subi	r12, r12, 4		# set up pointer to table  

	# program MCR with initial write command 
	lis		r9, MCR_UPMB_WRITE_INIT@h
	ori		r9, r9, MCR_UPMB_WRITE_INIT@l

UPMBInit:	
	lwzu	r8, 4(r12)			# get data from table 
	stw		r8, MDR(r4)		# store data to MD register 
	stw		r9, MCR(r4)		# issue write command to MCR register 
	addi	r9, r9, 1			# update UPMB address in write command 
	bdnz	UPMBInit

	# Make SDRAM Ready

	# Initialize Memory Periodic Timer  Prescalar Register, MPTPR  
	li		r12, MPTPR_INIT
	sth		r12, MPTPR(r4)

	# Initialize Machine B Mode Register, MBMR, 4 beats
	lis		r12, MBMR_4_INIT@h
	ori		r12, r12, MBMR_4_INIT@l
	stw		r12, MBMR(r4)

	# Map CS4 to SDRAM

	# program BR4 
	lis		r12, CS_BR4_INIT@h
	ori		r12, r12, CS_BR4_INIT@l 
	stw		r12, CS_BR4(r4)

	# program OR4 
	lis		r12, CS_OR4_INIT@h
	ori		r12, r12, CS_OR4_INIT@l 
	stw		r12, CS_OR4(r4)

	# program MAR 
	lis		r12, MAR_UPMB_INIT@h
	ori		r12, r12, MAR_UPMB_INIT@l 
	stw		r12, MAR(r4)

	# program MCR with setup
	lis		r12, MCR_UPMB_SETUP_INIT@h
	ori		r12, r12, MCR_UPMB_SETUP_INIT@l 
	# run setup
	stw		r12, MCR(r4)

	# Initialize Machine B Mode Register, MBMR, 8 beats
	lis		r12, MBMR_8_INIT@h
	ori		r12, r12, MBMR_8_INIT@l
	stw		r12, MBMR(r4)

	# program MCR with execute refresh
	lis		r12, MCR_UPMB_REFRESH_INIT@h
	ori		r12, r12, MCR_UPMB_REFRESH_INIT@l 
	# run refresh
	stw		r12, MCR(r4)

	# Initialize Machine B Mode Register, MBMR, back to 4 beats
	lis		r12, MBMR_4_INIT@h
	ori		r12, r12, MBMR_4_INIT@l
	stw		r12, MBMR(r4)

	#SDRAM is now ready to use

UPMBProgramEnd:
# End

CacheDisable:
	# Disable the instruction/data cache 
	lis		r12, IC_DISABLE@h		# load disable cmd 
	ori		r12, r12,IC_DISABLE@l
	isync
	mtspr	IC_CST, r12				# disable I cache 

	lis		r12, DC_DISABLE@h		# load disable cmd 
	ori		r12, r12, DC_DISABLE@l
	sync 
	mtspr	DC_CST, r12				# disable D cache 


# initialize the stack pointer, just in case
init_stack:
	lis		r1,__SP_INIT@h
	ori		r1,r1,__SP_INIT@l
	addi	r1,r1,-0x20

	# END OF INITIALIZATION  
	b _start	# location in crt0.s

# Should never get here, but in case we do...  
poststart:
	b		poststart			# loop forever   
	nop
	nop
	nop

# UPMA setup for MPC823FADS UPMA 4 MB DRAM
#
# MPC823 by HEB 9/26/99
#
UPMATable:
# single read.  (offset 0x0 in UPM RAM)  
	.long	0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04
	.long	0x00ffec00, 0x37ffec47, 0xffffffff, 0xffffffff
# burst read. (offset 0x8 in UPM RAM) 
	.long	0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c
	.long	0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44
	.long	0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00
	.long	0x3fffc847, 0xffffffff, 0xffffffff, 0xffffffff
# single write. (offset 0x18 in UPM RAM) 
	.long	0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# burst write. (offset 20 in UPM RAM) 
	.long	0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c
	.long	0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c
	.long	0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# refresh. (offset 30 in UPM RAM) 
	.long	0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06
	.long	0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# exception. (offset 3c in UPM RAM) 
	.long	0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff
#end of MPC823FADS UPMA programming
UPMATableEnd:

# UPMB setup for MPC823FADS UPMB 4 MB SDRAM
#
# MPC823 by HEB 10/03/99
#
# Initializations for Fujitsu MB811171622A-100 SDRAM
# for clocks up to 32 MHz
#
UPMBTable_32:
# single read.  (offset 0x0 in UPM RAM)  
	.long	0x0126cc04, 0x0fb98c00, 0x1ff74c45, 0xffffffff
	.long	0xffffffff, 0x1fe77c34, 0xefaabc34, 0x1fa57c35
# burst read. (offset 0x8 in UPM RAM) 
	.long	0x0026fc04, 0x10adfc00, 0xf0affc00, 0xf1affc00
	.long	0xefbbbc00, 0x1ff77c45, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# single write. (offset 0x18 in UPM RAM) 
	.long	0x0e26bc04, 0x01b93c00, 0x1ff77c45, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# burst write. (offset 20 in UPM RAM) 
	.long	0x0e26bc00, 0x10ad7c00, 0xf0affc00, 0xf0affc00
	.long	0xe1bbbc04, 0x1ff77c45, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# refresh. (offset 30 in UPM RAM) 
	.long	0x1ff5fc84, 0xfffffc04, 0xfffffc84, 0xfffffc05
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# exception. (offset 3c in UPM RAM) 
	.long	0x7ffffc07, 0xffffffff, 0xffffffff, 0xffffffff
#end of MPC823FADS UPMB programming
UPMBTable_32End:

# UPMB setup for MPC823FADS UPMB 4 MB SDRAM
#
# MPC823 by HEB 10/03/99
#
# Initializations for Fujitsu MB811171622A-100 SDRAM
# for clocks 32-50 MHz
#
UPMBTable_50:
# single read.  (offset 0x0 in UPM RAM)  
	.long	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00
	.long	0x1ff77c47, 0x1ff77c34, 0xefeabc34, 0x1fb57c35
# burst read. (offset 0x8 in UPM RAM) 
	.long	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00
	.long	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# single write. (offset 0x18 in UPM RAM) 
	.long	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# burst write. (offset 20 in UPM RAM) 
	.long	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
	.long	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# refresh. (offset 30 in UPM RAM) 
	.long	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04
	.long	0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff
	.long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# exception. (offset 3c in UPM RAM) 
	.long	0x7ffffc07, 0xffffffff, 0xffffffff, 0xffffffff
#end of MPC823FADS UPMB programming
UPMBTable_50End:

# == End of MPC823 Poweron Reset Initialization Assembly Source File ===== 
	.end