📄 bsestart.s
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#
# bsestart.s
#
# Barnett Systems Engineering
# MPC823 Poweron Reset Initialization Assembly Source File
#
# Author: Harry E. Barnett 9/27/99
# harryb@hbbse.com http://www.hbbse.com
#
# Version V1.00
#
#########################################################################
.list
.file "bsestart.s"
.title "BSE MPC823 Poweron Reset Init Assembly Source File"
.text
.align 2
# PPC register equivalents
rTOC .equ 2
XRTOC .equ 20
# Memory Mapped Register Offsets
CS_BR0 .equ 0x100
CS_BR1 .equ 0x108
CS_BR2 .equ 0x110
CS_BR4 .equ 0x120
CS_OR0 .equ 0x104
CS_OR1 .equ 0x10C
CS_OR2 .equ 0x114
CS_OR4 .equ 0x124
MAMR .equ 0x170
MAR .equ 0x164
MBMR .equ 0x174
MCR .equ 0x168
MDR .equ 0x17C
MPTPR .equ 0x17A
PISCR .equ 0x240
PISCRK .equ 0x340
PLPRCR .equ 0x284
PLPRCRK .equ 0x384
RTC .equ 0x224
RTCAL .equ 0x22C
RTCALK .equ 0x32C
RTCK .equ 0x324
RTCSC .equ 0x220
RTCSCK .equ 0x320
RTSEC .equ 0x228
RTSECK .equ 0x328
SCCR .equ 0x280
SCCRK .equ 0x380
SIUMCR .equ 0x000
SYPCR .equ 0x004
TBSCR .equ 0x200
TBSCRK .equ 0x300
# Initializations
CS_BR0_INIT .equ 0x02800001
CS_BR1_INIT .equ 0x02100001
CS_BR2_INIT .equ 0x00000001
CS_BR4_INIT .equ 0x030000C1
CS_OR0_INIT .equ 0xFFC00D34
CS_OR1_INIT .equ 0xFFFF8110
CS_OR2_INIT .equ 0xFFC00800
CS_OR4_INIT .equ 0xFFC00A00
DC_DISABLE .equ 0x04000000
DC_ENABLE .equ 0x02000000
# DEC_INIT_30 .equ 0x00008000 #~30 tick per second @ 25 MHz
DEC_INIT_30 .equ 0x0000F5C2 #~30 tick per second @ 48 MHz
DEC_INIT_MAX .equ 0x7FFFFFFF
# DER_INIT .equ 0xFFC3400F
DER_INIT .equ 0xFDC3400F #EXTIE disabled
ICTRL_INIT .equ 0x00000000
IC_DISABLE .equ 0x04000000
IC_ENABLE .equ 0x02000000
IMMR_INIT .equ 0xFF000000
KEY_UNLOCK .equ 0x55CCAA33
MAMR_INIT .equ 0xC0A21114
MAR_UPMB_INIT .equ 0x00000088
MBMR_4_INIT .equ 0xD0802114
MBMR_8_INIT .equ 0xD0802118
MCR_UPMB_REFRESH_INIT .equ 0x80808130
MCR_UPMB_SETUP_INIT .equ 0x80808105
MCR_UPMB_WRITE_INIT .equ 0x00808000
MPTPR_INIT .equ 0x0400
MSR_INIT .equ 0x00009002
MSR_INIT_NO_EE .equ 0x00001002
PISCR_INIT .equ 0x0082
PLPRCR_INIT .equ 0x00B0D000
RTCAL_INIT .equ 0xFFFFFFFF
RTCSC_INIT .equ 0x00D3
RTC_INIT .equ 0x00000000
RTSEC_INIT .equ 0xFFFFFFFF
SCCR_INIT .equ 0x01000000
SIUMCR_INIT .equ 0x00012440
SYPCR_INIT .equ 0xFFFFFF88
TBSCR_INIT .equ 0x00C3
# GLOBALS
.global poreset # start of system code
.global copyright
.global program_version
.extern DECIntr
.extern OSCtxSw
.extern _start
.entry poreset
.text
.align 2
# System Reset entry point: Offset 0x100
.org (0x100)
poreset:
b bsestart
program_version:
.string "Barnett Systems Engineering V0.4 11/08/99\0"
copyright:
.string "Copyright 1999 Barnett Systems Engineering Author: Harry E. Barnett\0"
# simple exception handlers, spinners
.org (0x200)
b .
.org (0x300)
b .
.org (0x400)
b .
.org (0x500)
b .
.if 0
ei_exc:
b EIEIntr
.endif
.org (0x600)
b .
# Program exception entry point
.org (0x700)
program_exc:
b . #Spin
.org (0x800)
b .
# Decrementer exception entry point 0x900
dec_exc:
.org (0x900)
b DECIntr
# System Call exception entry point 0xC00
.org (0xC00)
sc_exc:
b OSCtxSw
.org (0xD00)
trace_exc:
b .
.org (0xE00)
b .
.org (0x1000)
b .
.org (0x1100)
rfi
.org (0x1200)
rfi
.org (0x1300)
rfi
.org (0x1400)
rfi
.org (0x1C00)
b .
.org (0x1D00)
b .
.org (0x1E00)
b .
.org (0x1F00)
b .
.org 0x3000
# START OF INITIALIZATION
# Spotty chip initialization for the moment
bsestart:
# Setup Unlock Key register r5: r5 is reserved from here to end of module
lis r5, KEY_UNLOCK@h
ori r5, r5, KEY_UNLOCK@l
SPR_Init:
# Initialize MSR and SRR1
lis r12, MSR_INIT_NO_EE@h
ori r12, r12, MSR_INIT_NO_EE@l
mtmsr r12
mtspr SRR1, r12
# Initialize Instruction Support Control Register
lis r12, ICTRL_INIT@h
ori r12, r12, ICTRL_INIT@l
mtspr ICTRL, r12
# Initialize Debug Enable Register
lis r12, DER_INIT@h
ori r12, r12, DER_INIT@l
mtspr DER, r12
# Initialize Decrementer Register
lis r12, DEC_INIT_MAX@h
ori r12, r12, DEC_INIT_MAX@l
mtspr DEC, r12
# Initialize Interrupt Cause Register
# clear all interrupt causes by reading the ICR
mfspr r12, ICR
IMMR_Init:
# Initialize the IMMR register
# r4 is reserved from here to end of module
lis r4, IMMR_INIT@h
mtspr IMMR, r4 # initialize the IMMR register
mfspr r4, IMMR # read it back
rlwinm r4, r4, 0, 0, 15 # only high 16 bits count
ClockInit:
# Initialize System Clock Control Register
stw r5, SCCRK(r4) # Unlock
lis r12, SCCR_INIT@h
ori r12, r12, SCCR_INIT@l
stw r12, SCCR(r4)
# Initialize the PLL, Low Power, and Reset Control Register
stw r5, PLPRCRK(r4) # Unlock
lis r12, PLPRCR_INIT@h
ori r12, r12, PLPRCR_INIT@l
stw r12, PLPRCR(r4)
SIU_Init:
# Initialize SIU Module Configuration Register
lis r12, SIUMCR_INIT@h
ori r12, r12, SIUMCR_INIT@l
stw r12, SIUMCR(r4)
# Initialize the System Protection Control Register
lis r12, SYPCR_INIT@h
ori r12, r12, SYPCR_INIT@l
stw r12, SYPCR(r4)
SI_TimersInit:
# Initialize the Time Base Status and Control register
stw r5, TBSCRK(r4) # Unlock
li r12, TBSCR_INIT
sth r12, TBSCR(r4)
# Initialize Real Time Clock Register
stw r5, RTCK(r4) # Unlock
lis r12, RTC_INIT@h
ori r12, r12, RTC_INIT@l
stw r12, RTC(r4)
# Initialize Real Time Clock Status and Control Register
stw r5, RTCSCK(r4) # Unlock
li r12, RTCSC_INIT
sth r12, RTCSC(r4)
# Initialize Real Time Clock Alarm Register
stw r5, RTCALK(r4) # Unlock
lis r12, RTCAL_INIT@h
ori r12, r12, RTCAL_INIT@l
stw r12, RTCAL(r4)
# Initialize Real Time Clock Alarm Seconds Register
stw r5, RTSECK(r4) # Unlock
lis r12, RTSEC_INIT@h
ori r12, r12, RTSEC_INIT@l
stw r12, RTSEC(r4)
# Check...
lwz r12,RTSEC(r4)
# Initialize Periodic Interrupt Status and Control Register
stw r5, PISCRK(r4) # Unlock
li r12, PISCR_INIT
sth r12, PISCR(r4)
MEMC_Init:
# Initialize Memory Periodic Timer Prescalar Register, MPTPR
li r12, MPTPR_INIT
sth r12, MPTPR(r4)
# Initialize Memory Controller Base and Options registers
# Map CS0 to Flash
# program BR0
# BR0 - 0x00000001 0 Mb Base, GPCM, Valid
lis r12, CS_BR0_INIT@h
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