memmap.s

ucos下的driver的抽象层, 有了这一层porting将更容易

	TTL     Memory map for target-specific MMU initialisation    > memmap.s
	; ---------------------------------------------------------------------
	; This file provides the memory map table for MMU initialisation 
	; for the PID ARM720 board. The SETUP_MMU macro references this
	; table to build the TLBs on power-up.
	;
	; Copyright ARM Limited, 1998.
	; All Rights Reserved
	;

	INCLUDE bits.s
	INCLUDE sizes.s
	INCLUDE	platform.s
	INCLUDE	mmu_h.s

	; Note: Table must end with all zeros
	; WindowsCE uses a table of the same format, but without the access
	; word. If OEMAddressTable exists, but uHAL_Level1Table doesn't, the
	; MMU setup code should use the truncated format.
	;
	; MMU Mapping tables of the format:
	;
	; Virtual Address, Physical Address, Access Permissions, Area Size
	; Level 2 areas are more complex to define: 
	; Virt Addr, L2 Table & type, Phys Addr + L2 Access Perms, Area Size
   ;
	; MPU Mapping tables of the format:
	;
	; region number, base address, size and access permissions
	;
   ; Number of Level2 table entries in uHAL_AddressTable needs to be defined
   ; as LEVEL2_TABLE_ENTRIES in platform.[hs]

	AREA    |C$$code$$__mmutable|, CODE, READONLY

	LTORG

	EXPORT	uHAL_AddressTable	; Address map for MMUs
	EXPORT	uHAL_MappingTable	; Mapping for MPUs

uHAL_MappingTable

	; Define MPU regions/areas
	; Format is region number, base address, size and access permissions
	DCD	0, 0, MPU_SZ_4G, 0
	DCD	1, RAM_BASE, MPU_SZ_16M, DRAM_ACCESS
	DCD	2, FLASH_BASE, MPU_SZ_64M, FLASH_ACCESS
	DCD	3, FPGA_BASE, MPU_SZ_32M, IO_ACCESS
	DCD	4, IO_BASE, MPU_SZ_64M, IO_ACCESS
	DCD	0,	0,	0,	0	; End of Table (MUST BE ZEROS!)

uHAL_AddressTable

   IF :LNOT: :DEF: ARM7T
	
	; Map RAM 1-1 from RAM_BASE, cachable & bufferable
	DCD	RAM_BASE   , RAM_BASE   , DRAM_ACCESS,  RAM_SIZE

	; DCache clean space (actually the flash)
	DCD	CLEAN_BASE,  CLEAN_BASE,  DRAM_ACCESS , CLEAN_SIZE

	; Flash
	DCD	FLASH_BASE,  FLASH_BASE,  FLASH_ACCESS, FLASH_SIZE
	
	; FPGA
	DCD	FPGA_BASE,   FPGA_BASE,   IO_ACCESS,    FPGA_SIZE

	; I/O
	DCD	IO_BASE,     IO_BASE,   IO_ACCESS,      IO_SIZE

   ENDIF	
	; End of table (MUST be zeros) 
	DCD	0,	0,	0,	0

	END