platform.s

ucos下的driver的抽象层, 有了这一层porting将更容易

;/*****************************************************************************
; * Copyright (C) ARM Limited 1998. All rights reserved. 
; *****************************************************************************/
;/************************************************************************
;
;  PID address map
;
;	NOTE: This is a multi-hosted header file for use with uHAL and
;	      supported debuggers.
;
;************************************************************************/

 IF :LNOT: :DEF: __address_h
__address_h		EQU	1

PLATFORM_ID		EQU	0x00000040

; Common modules for uHAL can be included or excluded by changing these
; definitions. These can be over-ridden by the makefile/ARM project file
; provided the .h file can is rebuilt.
 IF :LNOT: :DEF: uHAL_BOOT
uHAL_BOOT		EQU	1
 ENDIF
 IF :LNOT: :DEF: uHAL_TIMERS
uHAL_TIMERS		EQU	1
 ENDIF
 IF :LNOT: :DEF: uHAL_INTERRUPTS
uHAL_INTERRUPTS		EQU	1
 ENDIF
 IF :LNOT: :DEF: uHAL_COMPLEX_IRQ
uHAL_COMPLEX_IRQ	EQU	1
 ENDIF
 IF :LNOT: :DEF: uHAL_PCI
uHAL_PCI		EQU	0
 ENDIF
 IF :LNOT: :DEF: uHAL_HEAP
uHAL_HEAP		EQU	1
uHAL_HEAP_BASE		EQU	SZ_256K
uHAL_HEAP_SIZE		EQU	SZ_128K
uHAL_STACK_BASE		EQU	SZ_512K
uHAL_STACK_SIZE		EQU	SZ_128K
 ENDIF

; /* memory size */
uHAL_MEMORY_SIZE	EQU	SZ_512K
PID7T_L1_TABLE_BASE	EQU	0x01004000

; /* The APB FPGA */
ICBase			EQU	0x0A000000
CTBase			EQU	0x0A800000
RPCBase			EQU	0x0B000000

; /* Remap and pause memory map */
RPC_Pause		EQU	0x00000000
RPC_Identification	EQU	0x00000010
RPC_ClearResetMap	EQU	0x00000020
RPC_ResetStatusSet	EQU	0x00000030
RPC_ResetStatusClear	EQU	0x00000034 

; /* IRQ/FIQ stuff */
IC_IRQStatus		EQU	0x00000000
IC_IRQRawStatus		EQU	0x00000004
IC_IRQEnable		EQU	0x00000008
IC_IRQEnableSet		EQU	0x00000008
IC_IRQEnableClear	EQU	0x0000000C

IC_FIQStatus		EQU	0x00000100
IC_FIQRawStatus		EQU	0x00000104
IC_FIQEnable		EQU	0x00000108
IC_FIQEnableSet		EQU	0x00000108
IC_FIQEnableClear	EQU	0x0000010C
IC_FIQSource		EQU	0x00000114
	
MAXIRQNUM		EQU	15
MAXFIQNUM		EQU	15
MAXSWINUM		EQU	15

NR_IRQS			EQU	(MAXIRQNUM + 1)

RAM_BASE		EQU	0
RAM_SIZE		EQU	0x01000000
FLASH_BASE		EQU	0x04000000
FLASH_SIZE		EQU	0x04000000
CLEAN_BASE		EQU	FLASH_BASE
CLEAN_SIZE		EQU	FLASH_SIZE
FPGA_BASE		EQU	0x0A000000
FPGA_SIZE		EQU	0x02000000
IO_BASE			EQU	0x0C000000
IO_SIZE			EQU	0x04000000
	
; Number of Level2 table entries in uHAL_AddressTable
L2_TABLE_ENTRIES	EQU	1

; /* UART */
; /* define it so that it only ever uses one port */
HOST_COMPORT		EQU	ST16C552_IO_BASE 
SEMIHOSTED_COMPORT		EQU	HOST_COMPORT
OS_COMPORT		EQU	HOST_COMPORT

; /* Values to set given baud rates */
DEFAULT_HOST_BAUD	EQU	ARM_BAUD_9600
DEFAULT_OS_BAUD		EQU	ARM_BAUD_38400

;#define IO_MAPADDRESS(a)	(((unsigned int) a << 2) | IO_BASE)
;#define _MapAddress(a)		IO_MAPADDRESS(a)
;#define IO_READ(p)		(*(unsigned char *)(IO_MAPADDRESS(p)))
;#define IO_WRITE(p, c)		(*(unsigned char *)(IO_MAPADDRESS(p)) = c)

; /* This board uses the st16c552 UART as stdio */
ST16C552_IO_BASE	EQU	(IO_BASE + 0x01800000)

;/* UART primitives */
;#define GET_STATUS(p)	(*(volatile unsigned char *)((p) + ST16C552_LSR))
;#define RX_DATA(s)     ((s & LSRRxData) != 0)
;#define GET_CHAR(p)	(*(volatile unsigned char *)((p) + ST16C552_RHRTHR))
;#define TX_READY(s)    ((s & LSRTxHoldEmpty) != 0)
;#define PUT_CHAR(p,c)  (*(volatile unsigned char *)((p) + ST16C552_RHRTHR) = (c))
		
;/* ST16C552 specific stuff */
;/*
; * Clock Divisors for various Baud rates (assuming that
; * the PID is using a 1.843 MHz clock for the UART)
; */
ARM_BAUD_1200	EQU	0x0060
ARM_BAUD_2400	EQU	0x0030
ARM_BAUD_4800	EQU	0x0018
ARM_BAUD_9600	EQU	0x000c
ARM_BAUD_19200	EQU	0x0006
ARM_BAUD_38400	EQU	0x0003
ARM_BAUD_57600	EQU	0x0002
ARM_BAUD_115200	EQU	0x0001

;/*
; * Register offsets
; */
ST16C552_RHRTHR		EQU	0x00
ST16C552_IER		EQU	0x04
ST16C552_ISRFCR		EQU	0x08
ST16C552_LCR		EQU	0x0C
ST16C552_MCR		EQU	0x10
ST16C552_LSR		EQU	0x14
ST16C552_MSR		EQU	0x18
ST16C552_SPR		EQU	0x1C
	
;/*
; * Line Status Register bits
; */
LSRRxData       EQU	(1 << 0)
LSROverrun      EQU	(1 << 1)
LSRParity       EQU	(1 << 2)
LSRFraming      EQU	(1 << 3)
LSRBreak        EQU	(1 << 4)
LSRTxHoldEmpty  EQU	(1 << 5)
LSRTxEmpty      EQU	(1 << 6)
LSRFIFOError    EQU	(1 << 7)

	
; /* LEDs */
uHAL_NUM_OF_LEDS		EQU	0
ALL_LEDS		EQU	0
;#define uHAL_LED_MASKS	{ 0 }
;#define uHAL_LED_OFFSETS	{ 0 }
 IF :LNOT: :DEF: HIGH
HIGH			EQU	1
 ENDIF
uHAL_LED_ON		EQU	1
uHAL_LED_OFF		EQU	0

; /* Timer stuff */
TIMERBase		EQU	0x0A800000
TIMER_LOAD		EQU	0x00000000
TIMER_VALUE		EQU	0x00000004
TIMER_CONTROL		EQU	0x00000008
TIMER_CLEAR		EQU	0x0000000C
	
OS_TIMER			EQU	1
MAX_TIMER			EQU	1

; The irq numbers of the individual timers
;#define TIMER_VECTORS	{ 0, 4}
;16Mhz clock, /16 divider, = 1000
mSEC_1			EQU	1000
MAX_PERIOD		EQU	0xFFFF	


 ENDIF

	END