📄 driver.s
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;/*****************************************************************************
; * Copyright (C) ARM Limited 1998. All rights reserved.
; *****************************************************************************/
;/*****************************************************************************
;
; PID specific assembly source code.
;
;******************************************************************************/
INCLUDE bits.s
INCLUDE sizes.s
INCLUDE platform.s
INCLUDE mmu_h.s
GET target.s
EXPORT uHALir_InitTargetMem ; Initialise memory
EXPORT uHALir_FindRAMTop ; Find top of memory
IMPORT uHALir_EnterLockedSvcMode ; Enter Supervisor mode & disable IRQ.
IMPORT uHALir_ExitSvcMode ; Exit Supervisor mode.
IMPORT uHALiv_TopOfMemory ; Top of RAM.
EXPORT Level1tab
EXPORT Level2tab_ROM
EXPORT MPUMaptab
KEEP
AREA |C$$code$$__pid|, CODE, READONLY
; -------------------------------------------------------------------
; Routine to initialise the target-specific RAM:
;
; See INIT_RAM macro for description
; NOTE: lr contains return address
; a1 returns top of memory
uHALir_InitTargetMem
;; Initialise the DRAM (if present)
INIT_RAM a1,v1,v2,v3,v4
LDR a1, =uHAL_MEMORY_SIZE
GET_RAMSIZE a1,v1,v2,v3,v4
MOV pc, lr ; All done, return
uHALir_FindRAMTop
STMFD r13!,{v1,v2,v3,v4}
GET_RAMSIZE a1,v1,v2,v3,v4
LDMFD r13!,{v1,v2,v3,v4}
MOV pc, lr ; All done, return
AREA uHAL_TTentries, DATA, NOINIT, ALIGN=14
;------------------------------------------------------------------
; MMU lookup tables. Because the SETUPMMU macro is shared with
; semihosted, it uses simple names, these are aliased to uHAL
; standard for internal use.
;
; NOTE: These areas are declared even for processors without MMUs
; 4-byte entries,1MB sections
uHALiv_Level1tab
Level1tab % (L1_TABLE_ENTRIES * 4)
; 4-byte entries, 64kB pages; x16 alias
uHALiv_Level2tab_ROM
Level2tab_ROM % (L2_TABLE_ENTRIES * L2_ENTRY_SIZE * 4)
; 4-byte entries, 8 regions + 3 flags
uHALiv_MPUMaptab
MPUMaptab % (MPU_TABLE_ENTRIES * 4)
END
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