lcd.h

sharp触摸屏测试代码

/*
 *  NOTE:NO_VM
 *
 */

#ifndef LCD_404
#define LCD_404




typedef  unsigned long u32;
typedef  unsigned char  u8;


/*
 * Color LCD Controller registers
 */
typedef struct {
    u32	timing0;		/* Horizontal axis panel control	*/
    u32	timing1;		/* Vertical axis panel control		*/
    u32	timing2;		/* clock and signal polarity control	*/
    u32	timing3;		/* line end control			*/
    u32	upbase;			/* upper panel frame base address	*/
    u32	lpbase;			/* lower panel frame base address	*/
    u32	intrEnable;		/* interrupt enable mask		*/
    volatile u32	control;		/* LCD panel pixel parameters		*/
    volatile u32	rawIntrStatus;		/* raw interrupt status			*/
    volatile u32	maskedIntrStatus;	/* masked interrupt status		*/
    volatile u32	upcurr;			/* upper panel current address		*/
    volatile u32	lpcurr;			/* lower panel current address		*/
    volatile u32	lpoverflow;		/* SDRAM fb base			*/
    volatile u32	reservedcc[115];	/* reserved				*/
    volatile u32	palette[128];		/* 256 x 16-bit color palette		*/
} lcdRegs_t;




#define _BIT(n) (1 << (n))
#define _SBF(f,v) ((v) << (f))



/*
 * LCDTiming0 Register Bit Field constants
 *
 * NOTE: Ensure the argument to the following macros is greater
 * than zero.
 */

#define LCD_TIMING0_HBP(n)	_SBF(24,((n)-1))		/* Horiz Back Porch */ 
#define LCD_TIMING0_HFP(n)	_SBF(16,((n)-1))		/* Horiz Front Porch */ 
#define LCD_TIMING0_HSW(n)	_SBF(8,((n)-1))			/* Horiz sync Pulse Width */ 
#define LCD_TIMING0_PPL(n)	_SBF(2,((((n)/16)-1)&0x3F))	/* Pixels per line */ 

/*
 * LCDTiming1 Register Bit Field constants
 *
 * NOTE: Ensure the argument to the following macros is greater
 * than zero.
 */ 
#define LCD_TIMING1_VBP(n)	_SBF(24,(n))		/* Vertical Back Porch */ 
#define LCD_TIMING1_VFP(n)	_SBF(16,(n))		/* Vertical Front Porch */ 
#define LCD_TIMING1_VSW(n)	_SBF(10,(n))		/* Vertical Synchronization Pulse */ 
#define LCD_TIMING1_LPP(n)	_SBF(0,((n)-1))		/* Lines per Panel */ 

/*
 * LCDTiming2 Register Bit Field constants
 *
 * NOTE: Ensure the argument to the following macros is greater
 * than two.
 */ 
#define LCD_TIMING2_BCD 	_BIT(26)		/* Bypass Pixel Clock Divider */
#define LCD_TIMING2_CPL(n)	_SBF(16,((n)-1)&0x3FF)	/* Clocks Per Line */ 
#define LCD_TIMING2_IOE		_BIT(14)		/* Invert Output Enable */ 
#define LCD_TIMING2_IPC		_BIT(13)		/* Invert Panel Clock */ 
#define LCD_TIMING2_IHS 	_BIT(12)		/* Invert Horizontal Synchronization */ 
							/* set == HSYNC is active low	     */
#define LCD_TIMING2_IVS		_BIT(11)		/* Invert Vertical Synchronization */ 
							/* set == VSYNC is active low	     */
#define LCD_TIMING2_ACB(n)	_SBF(6,((n)-1))		/* AC Bias Pin Frequency */ 
#define LCD_TIMING2_CLKSEL	 _BIT(5)		/* Clock Selector */ 
#define LCD_TIMING2_PCD(n)	_SBF(0,((n)-2))		/* Panel Clock Divisor */ 


/*
 * LCDTiming3 Register Bit Field constants
 *
 * NOTE: Ensure the argument to the following macros is greater
 * than one.
 */ 
#define LCD_TIMING3_LEE		_BIT(16)		/* Line End Enable */ 
#define LCD_TIMING3_LED(n)	_SBF(0,((n)-1))		/* Line End Signal Delay */ 


/*
 * intrEnable, rawIntrStatus, maskedIntrStatus bit field positions
 */
#define LCD_STATUS_MBERROR	_BIT(4)			/* Master Bus Error */ 
#define LCD_STATUS_VCOMP 	_BIT(3)			/* Vertical Compare */ 
#define LCD_STATUS_LNBU 	_BIT(2)			/* LCD Next addr. Base Update*/ 
#define LCD_STATUS_FUF 		_BIT(1)			/* FIFO underflow */ 


/*
 * Control Register Bit Field constants
 */ 
#define LCD_CTRL_WATERMARK	_BIT(16)		/* LCD DMA FIFO Watermark Level */ 
#define LCD_CTRL_LDMAFIFOTME	_BIT(15)		/* LCD DMA FIFO Test Mode Enable */ 

#define LCD_CTRL_VCOMP(n)	_SBF(12,((n)&0x3))	/* Generate interrupt at:	*/
#define LCD_CTRL_VCOMP_SVS	_SBF(12,0)		/*   start of vertical sync	*/
#define LCD_CTRL_VCOMP_SBP	_SBF(12,1)		/*   start of back porch 	*/
#define LCD_CTRL_VCOMP_SAV	_SBF(12,2)		/*   start of active video	*/
#define LCD_CTRL_VCOMP_SFP	_SBF(12,3)		/*   start of front porch	*/

#define LCD_CTRL_PWR		_BIT(11)		/* LCD Power Enable		*/ 
#define LCD_CTRL_BEPO		_BIT(10)		/* Big Endian Pixel Order	*/ 
#define LCD_CTRL_BEBO		_BIT(9)			/* Big Endian Byte Order	*/ 
#define LCD_CTRL_BGR		_BIT(8)			/* Swap Red and Blue (RGB to BGR) */ 
#define LCD_CTRL_DUAL		_BIT(7)			/* Dual Panel STN		*/ 
#define LCD_CTRL_MON8		_BIT(6)			/* Monochrome LCD has 8-bit interface */ 
#define LCD_CTRL_TFT 		_BIT(5)			/* TFT LCD			*/ 

#define LCD_CTRL_BW_COLOR	_SBF(4,0)		/* STN LCD is Color		*/ 
#define LCD_CTRL_BW_MONO	_SBF(4,1)		/* STN LCD is Monochrome	*/

#define LCD_CTRL_BPP1		_SBF(1,0)		/* Bits per pixel		*/ 
#define LCD_CTRL_BPP2		_SBF(1,1)
#define LCD_CTRL_BPP4		_SBF(1,2)
#define LCD_CTRL_BPP8		_SBF(1,3)
#define LCD_CTRL_BPP16		_SBF(1,4)
#define LCD_CTRL_BPP24		_SBF(1,5)

#define LCD_CTRL_ENABLE		_BIT(0)			/* LCD Controller Enable	*/ 


typedef struct {
    volatile u32 setup;					/* Setup		*/ 
    volatile u32 control;				/* Control		*/ 
    volatile u32 timing1;				/* HR-TFT Timing 1	*/ 
    volatile u32 timing2;				/* HR-TFT Timing 2	*/ 
} lcdicpRegs_t;



/*
 * LCDICP Setup Register Bit Fields
 *
 * NOTE: Ensure the argument to the following macros is greater
 * than zero.
 */ 
#define	LCDICP_SETUP_MODE_BYPASS	_SBF(0,0)
#define	LCDICP_SETUP_MODE_HRTFT		_SBF(0,1)
#define	LCDICP_SETUP_MODE_DMTN		_SBF(0,2)
#define	LCDICP_SETUP_HORIZ_REVERSE	_SBF(2,0)
#define	LCDICP_SETUP_HORIZ_NORMAL	_SBF(2,1)
#define	LCDICP_SETUP_VERT_REVERSE	_SBF(3,0)
#define	LCDICP_SETUP_VERT_NORMAL	_SBF(3,1)
/* Calculates bit field value from actual pixels per line */ 
#define LCDICP_SETUP_PPL(n)		_SBF(4,((n)-1))
#define LCDICP_SETUP_POWER		_BIT(13)	/* lh7a400 only */

#define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active	*/
#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/

/*
 * LCDICP Control Register Bit Fields
 */ 
#define LCDICP_CONTROL_SPSEN		_BIT(0)
#define LCDICP_CONTROL_CLSEN		_BIT(1)
#define LCDICP_CONTROL_UBLEN		_BIT(2)
#define LCDICP_CONTROL_DISP		_BIT(3)
#define LCDICP_CONTROL_EN0		_BIT(4)
#define LCDICP_CONTROL_EN1		_BIT(5)
#define LCDICP_CONTROL_EN2		_BIT(6)
#define LCDICP_CONTROL_EN3		_BIT(7)


/*
 * LCDICP Timing 1 Register Bit Fields
 *
 * NOTE: Ensure the argument to the following macros is greater
 * than zero.
 */ 
#define LCDICP_TIMING1_LPDEL(n)		_SBF(0,((n)-1)&0xF)
#define LCDICP_TIMING1_REVDEL(n)	_SBF(4,((n)-1)&0xF)
#define LCDICP_TIMING1_PSDEL(n)		_SBF(8,((n)-1)&0xF)
#define LCDICP_TIMING1_CLSDEL(n)	_SBF(8,((n)-1)&0xF)


/*
 * LCDICP Timing 2 Register Bit Fields
 *
 * NOTE: Ensure the argument to the following macros is greater
 * than zero.
 */ 
#define LCDICP_TIMING2_PSDEL2(n)	_SBF(0,((n)-1)&0x1FF)
#define LCDICP_TIMING2_CLSDEL2(n)	_SBF(0,((n)-1)&0x1FF)
#define LCDICP_TIMING2_SPLVALUE(n)	_SBF(9,((n)-1)&0x7F)


/*
 * This structure describes the machine which we are running on.
 */
struct fb_info {
//	char panelname;
//	u32 type;
	u32		pixclock;

	u32		xres;
	u32		yres;

	u32		bpp;
	
	u8		hsync_len;		/* horiz sync pulse width	*/
	u8		left_margin;		/* horiz back porch		*/
	u8		right_margin;		/* horiz front porch		*/

	u8		vsync_len;		/* vertical sync pulse width	*/
	u8		upper_margin;		/* vertical back porch		*/
	u8		lower_margin;		/* vertical front porch		*/

	u8		sync;

	u32		cmap_greyscale:1,
			cmap_inverse:1,
			cmap_static:1,
			unused:29;

	u32		LCDtiming2;
	u32		LCDtiming3;
	u32		LCDcontrol;
	u32		LCDICPsetup;
	u32		LCDICPcontrol;
	u32		LCDICPtiming1;
	u32		LCDICPtiming2;
	char *		panel_name;
};






#endif