lh7a400_mmu.i

sharp触摸屏测试代码

/*
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Workfile:   LH7A400_mmu.i  $
; $Revision:   1.2  $
; $Author:   BarnettH  $
; $Date:   May 31 2002 15:48:00  $
;
; Project:  LH7A400
;
; Description:
;   LH7A400 MMU coprocessor definitions
;   (ARM assembly language include file)
; 
; Notes:
;   (1) MCR/MRC{cond} P15, opcode_1, Rd, CRn, CRm, opcode_2
;
; References:
;   (1) ARM922T Technical Reference Manual, ARM DDI 0184B.
;
; $Log:   //smaicnt2/pvcs/VM/CHIPS/archives/SOC/LH7A400/Processor/LH7A400_mmu.i-arc  $
;
;   Rev 1.2   May 31 2002 15:48:00   BarnettH
;Added MMU_CONTROL_B bit
;
;   Rev 1.1   May 08 2002 14:54:08   BarnettH
;Added Clocking Mode Bit Field per Table 2-11
;
;   Rev 1.0   Apr 11 2002 11:23:10   BarnettH
;Initial revision.
;
; SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
; OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
; AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
; SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
;
; SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
; FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
; SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
; FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
;
; COPYRIGHT (C) 2001  SHARP MICROELECTRONICS OF THE AMERICAS INC.
;                        CAMAS, WA
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; MMU, Coprocessor Definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
*/
/*
#define SYS_CONTROL_CP    p15 ;CP 15
#define MMU_CP            p15;CP 15
#define CACHE_CP          p15;CP 15
*/
/*; Valid CP15 registers*/
/*
#define MMU_REG_ID           c0;CN 0
#define MMU_REG_CACHE_TYPE   c0;CN 0
#define MMU_REG_CONTROL      c1;CN 1
#define MMU_REG_TTB          c2;CN 2  ; Translation Table Base Address
#define MMU_REG_DAC          c3;CN 3  ; Domain Access Control
#define MMU_REG_FS           c5;CN 5  ; Fault Status
#define MMU_REG_FA           c6;CN 6  ; Fault Address
#define MMU_REG_CACHE_OP     c7;CN 7  ; Cache Operations
#define MMU_REG_TLB_OP       c8;CN 8  ; Translation Lookaside Buffer Operation
#define MMU_REG_CACHE_LOCK   c9;CN 9  ; Cache Lockdown
#define MMU_REG_TLB_LOCK     c10;CN 10 ; TLB Lockdown
#define MMU_REG_FCSE_PID     c13;CN 13 ; Fast Context Switch Extension
*/
/*; Control register bits*/
.equ MMU_CONTROL_M        , (1 << 0)   /*; MMU Enable*/
.equ MMU_CONTROL_A        , (1 << 1)   /*; Alignment Fault*/
.equ MMU_CONTROL_C        , (1 << 2)   /*; Data Cache*/
.equ MMU_CONTROL_B        , (1 << 7)   /*; Endianess*/
.equ MMU_CONTROL_S        , (1 << 8)   /*; System Protection*/
.equ MMU_CONTROL_R        , (1 << 9)   /*; ROM Protection*/
.equ MMU_CONTROL_I        , (1 << 12)  /*; Instruction Cache*/
.equ MMU_CONTROL_V        , (1 << 13)  /*; Exception Vector location*/
.equ MMU_CONTROL_RR       , (1 << 14)  /*; Round Robin Replacement*/
.equ MMU_CONTROL_NF       , 0x40000000  /*; Not FastBus*/
.equ MMU_CONTROL_IA       , 0x80000000  /*; Asynchronous Clock Select*/
/*; Clocking Mode Bit Field per Table 2-11*/
.equ MMU_CONTROL_FASTBUS_CLOCK  , (0)
.equ MMU_CONTROL_SYNCH_CLOCK    , (MMU_CONTROL_NF)
.equ MMU_CONTROL_ASYNCH_CLOCK   , (MMU_CONTROL_IA | MMU_CONTROL_NF)

/*; Convenient ,'s*/
.equ MMU_ENABLE              , (MMU_CONTROL_M)
.equ MMU_ENABLE_CACHE        , (MMU_CONTROL_M | MMU_CONTROL_C | MMU_CONTROL_I)

.equ MMU_CONTROL_ALL_BITS    , (MMU_CONTROL_M | MMU_CONTROL_A | MMU_CONTROL_C | MMU_CONTROL_B | MMU_CONTROL_S | MMU_CONTROL_R | MMU_CONTROL_I | MMU_CONTROL_V | MMU_CONTROL_RR | MMU_CONTROL_NF | MMU_CONTROL_IA)

/*
; Small page size - 4KB
; Large page size - 64KB
; Section size - 1MB
*/
.equ SMALL_PAGE_SIZE      ,      (0x400 * 4)
.equ LARGE_PAGE_SIZE      ,      (0x4000 * 4)
.equ SECTION_SIZE         ,      (0x40000 * 4)

/*
; Small page tables and Large page tables are the same size,
; 1024 bytes or 256 entries
; Large page tables have each of 16 entries replicated 16 times
; in succeeding memory locations
*/
.equ PAGE_TABLE_SIZE      ,      (0x100 * 4) /*; 256 entries*/
.equ TRANS_TABLE_SIZE     ,      (0x1000 * 4)/*; 4096 entries*/

/*
; N.B.: Translation table must be based on a 16KB boundary.
;       Page tables must be based on 1KB boundaries.
*/