lh7a400_intc.h

sharp触摸屏测试代码

/**********************************************************************
 *	$Workfile:   lh7a400_intc.h  $
 *	$Revision:   1.3  $
 *	$Author:   BarnettH  $
 *	$Date:   Jun 19 2002 18:00:36  $
 *
 *	Project: LH7A400 IP headers
 *
 *	Description:
 *      This file contains the structure definitions and manifest
 *      constants for the LH7A400 component:
 *      	Interrupt Controller
 *
 *	References:
 *		(1) Sharp LH7A400 Universal SoC User's Guide
 *
 *	Revision History:
 *	$Log:   //smaicnt2/pvcs/VM/CHIPS/archives/SOC/LH7A400/Processor/lh7a400_intc.h-arc  $
 * 
 *    Rev 1.3   Jun 19 2002 18:00:36   BarnettH
 * Changed register names
 * Added suffix of _BIT to the names of bit position constants.
 * Changed definition of bit pattern constants to use bit position
 * constants and _BIT(n) macro.
 * 
 *    Rev 1.2   Jun 05 2002 17:56:50   MaysR
 * Moved defines for interrupt controller bits here from LH7A400_map.h
 * 
 *    Rev 1.1   Apr 01 2002 19:49:40   SuryanG
 * Added legal disclaimer. Changed register names to lowercase.
 * 
 *    Rev 1.0   Oct 04 2001 14:32:42   BarnettH
 * Initial revision.
 * 
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *********************************************************************/

#ifndef LH7A400_INTC_H
#define LH7A400_INTC_H

#include "SMA_types.h"

/*
 * Interrupt Controller Module Register Structure
 */ 

typedef struct 
{
	volatile UNS_32		status;
	volatile UNS_32		rawstatus;
	volatile UNS_32		enableset;
	volatile UNS_32		enableclear;
} INTCREGS;

/**********************************************************************
 * The bit fields of the following registers have implementation
 * specific meaning, and must be defined at the implementation level.
 *
 * 		status		-Interrupt Status
 * 		rawstatus	-Interrupt RawStatus
 * 		enableset	- Enable Set
 * 		enableclear	- Enable Clear
 *
 * The following definitions for these registers are generic,
 * i.e., they are implementation independent. They can be used to
 * create implementation specific macros.
 *********************************************************************/ 
/**********************************************************************
 * Interrupt Controller Register Bit Fields
 *********************************************************************/ 

/* INTC Interrupt Sources */
#define INTC_GPIO0FIQ_BIT       0  
#define INTC_BLINTR_BIT         1
#define INTC_WEINTR_BIT         2
#define INTC_MCINTR_BIT         3
#define INTC_CSINTR_BIT         4
#define INTC_GPIO1INTR_BIT      5
#define INTC_GPIO2INTR_BIT      6
#define INTC_GPIO3INTR_BIT      7
#define INTC_TC1OINTR_BIT       8
#define INTC_TC2OINTR_BIT       9
#define INTC_RTCMINTR_BIT       10
#define INTC_TICKINTR_BIT       11
#define INTC_UART1INTR_BIT      12
#define INTC_UART2INTR_BIT      13
#define INTC_LCDINTR_BIT        14
#define INTC_SSEOTINTR_BIT      15
#define INTC_UART3INTR_BIT      16
#define INTC_SCIINTR_BIT        17
#define INTC_AACINTR_BIT        18
#define INTC_MMCINTR_BIT        19
#define INTC_USBINTR_BIT        20
#define INTC_DMAINTR_BIT        21
#define INTC_TC3OINTR_BIT       22
#define INTC_GPIO4INTR_BIT      23
#define INTC_GPIO5INTR_BIT      24
#define INTC_GPIO6INTR_BIT      25
#define INTC_GPIO7INTR_BIT      26
#define INTC_BMIINTR_BIT        27

#define INTC_GPIO0FIQ           _BIT(INTC_GPIO0FIQ_BIT)
#define INTC_BLINTR             _BIT(INTC_BLINTR_BIT)
#define INTC_WEINTR             _BIT(INTC_WEINTR_BIT)
#define INTC_MCINTR             _BIT(INTC_MCINTR_BIT)
#define INTC_CSINTR             _BIT(INTC_CSINTR_BIT)
#define INTC_GPIO1INTR          _BIT(INTC_GPIO1INTR_BIT)
#define INTC_GPIO2INTR          _BIT(INTC_GPIO2INTR_BIT)
#define INTC_GPIO3INTR          _BIT(INTC_GPIO3INTR_BIT)
#define INTC_TC1OINTR           _BIT(INTC_TC1OINTR_BIT)
#define INTC_TC2OINTR           _BIT(INTC_TC2OINTR_BIT)
#define INTC_RTCMINTR           _BIT(INTC_RTCMINTR_BIT)
#define INTC_TICKINTR           _BIT(INTC_TICKINTR_BIT)
#define INTC_UART1INTR          _BIT(INTC_UART1INTR_BIT)
#define INTC_UART2INTR          _BIT(INTC_UART2INTR_BIT)
#define INTC_LCDINTR            _BIT(INTC_LCDINTR_BIT)
#define INTC_SSEOTINTR          _BIT(INTC_SSEOTINTR_BIT)
#define INTC_UART3INTR          _BIT(INTC_UART3INTR_BIT)
#define INTC_SCIINTR            _BIT(INTC_SCIINTR_BIT)
#define INTC_AACINTR            _BIT(INTC_AACINTR_BIT)
#define INTC_MMCINTR            _BIT(INTC_MMCINTR_BIT)
#define INTC_USBINTR            _BIT(INTC_USBINTR_BIT)
#define INTC_DMAINTR            _BIT(INTC_DMAINTR_BIT)
#define INTC_TC3OINTR           _BIT(INTC_TC3OINTR_BIT)
#define INTC_GPIO4INTR          _BIT(INTC_GPIO4INTR_BIT)
#define INTC_GPIO5INTR          _BIT(INTC_GPIO5INTR_BIT)
#define INTC_GPIO6INTR          _BIT(INTC_GPIO6INTR_BIT)
#define INTC_GPIO7INTR          _BIT(INTC_GPIO7INTR_BIT)
#define INTC_BMIINTR            _BIT(INTC_BMIINTR_BIT)

/**********************************************************************
 * Defines for block access to interrupt sources
 *********************************************************************/ 

#define INTC_ALL_FIQS ( \
                        INTC_GPIO0FIQ | \
                        INTC_BLINTR | \
                        INTC_WEINTR | \
                        INTC_MCINTR)

#define INTC_ALL_IRQS ( \
                        INTC_CSINTR | \
                        INTC_GPIO1INTR | \
                        INTC_GPIO2INTR | \
                        INTC_GPIO3INTR | \
                        INTC_TC1OINTR | \
                        INTC_TC2OINTR | \
                        INTC_RTCMINTR | \
                        INTC_TICKINTR | \
                        INTC_UART1INTR | \
                        INTC_UART2INTR | \
                        INTC_LCDINTR | \
                        INTC_SSEOTINTR | \
                        INTC_UART3INTR | \
                        INTC_SCIINTR | \
                        INTC_AACINTR | \
                        INTC_MMCINTR | \
                        INTC_USBINTR | \
                        INTC_DMAINTR | \
                        INTC_TC3OINTR | \
                        INTC_GPIO4INTR | \
                        INTC_GPIO5INTR | \
                        INTC_GPIO6INTR | \
                        INTC_GPIO7INTR | \
                        INTC_BMIINTR)

#define INTC_ALL_INTS (INTC_ALL_FIQS | INTC_ALL_IRQS)

/**********************************************************************
 * Interrupt Enable Set, Interrupt Enable Clear Registers Bit Fields
 *********************************************************************/ 
#define INTC_INT_ENABLE(n)		_BIT(n)
#define INTC_INT_CLEAR(n)		_BIT(n)

#endif /* LH7A400_INTC_H */