📄 lh7a400_clksc.h
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/**********************************************************************
* $Workfile: LH7A400_clksc.h $
* $Revision: 1.9 $
* $Author: MaysR $
* $Date: Jun 20 2002 11:08:56 $
*
* Project: LH7A400 headers
*
* Description:
* This file contains the structure definitions and manifest
* constants for the LH7A400 component:
* Clock and State Controller
*
* References:
* (1) Sharp LH7A400 Universal SoC User's Guide
*
* Revision History:
* $Log: //smaicnt2/pvcs/VM/CHIPS/archives/SOC/LH7A400/Processor/lh7a400_clksc.h-arc $
*
* Rev 1.9 Jun 20 2002 11:08:56 MaysR
* Restored ".._BIT" constants, used by CSC driver.
*
* Rev 1.8 Jun 14 2002 13:20:26 BarnettH
* Eliminated 'xxx_BIT' definitions, and re-defined the 'xxx_FLG'
* definitions accordingly.
* Revised CLKSET_xxx macros to use the _SBF macro.
* Set up a "System Clocks" section.
* Moved definitions to establish the clkset register bit pattern
* for forseeable combinations desired clock frequenies from ...evb.h
* into this file.
* Defined CLKSET_DEFAULT in this file.
*
* Rev 1.7 Apr 01 2002 15:08:54 SuryanG
* Added legal disclaimer.
*
* Rev 1.6 Nov 28 2001 11:09:48 SuryanG
* Added apbwait register to clksc structure.
* Added APB_NO_WRITE_WAIT macro definition.
* Corrected PWRCNT_PRGCLK macro definition.
*
* Rev 1.5 Nov 14 2001 17:23:28 KovitzP
* Fixed typos on definition of USB frequency CLKSC_USB_CLK
*
* Rev 1.4 Nov 12 2001 17:51:26 KovitzP
* corrected typo in symbol CLKSC_TIMER_SEL0_CLK
*
* Rev 1.3 Nov 12 2001 17:28:36 KovitzP
* added derived clocks constants
*
* Rev 1.2 Nov 08 2001 17:02:30 SuryanG
* Corrected PWRSR_CHIPID define and added define for PWRSR_CHIPMAN.
*
* Rev 1.1 Oct 31 2001 13:45:56 SuryanG
* Corrected bitmask for PWRSR_RTCDIV
*
* Rev 1.0 Oct 04 2001 14:32:40 BarnettH
* Initial revision.
*
* SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
* OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
* AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
* SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
*
* SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
* FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
* SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
* FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
*
* COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
* CAMAS, WA
*********************************************************************/
#ifndef LH7A400_CLKSC_H
#define LH7A400_CLKSC_H
#include "SMA_types.h"
/**********************************************************************
* Clock and State Controller Structure
*********************************************************************/
typedef struct {
volatile UNS_32 pwrsr; /* Power/state control status */
volatile UNS_32 pwrcnt; /* Clock/debug control status */
volatile UNS_32 halt; /* Read to Enter Idle mode */
volatile UNS_32 stby; /* Read to Enter Standby mode */
volatile UNS_32 bleoi; /* Clear low battery interrupt */
volatile UNS_32 mceoi; /* Clear media changed interrupt */
volatile UNS_32 teoi; /* Clear tick interrupt */
volatile UNS_32 stfclr; /* Clear Nbflg, rstflg, pfflg, cldflg */
volatile UNS_32 clkset; /* Clock speed control */
volatile UNS_32 scrreg0; /* Scratch Register 0 */
volatile UNS_32 scrreg1; /* Scratch Register 1 */
volatile UNS_32 clktest; /* TEST register */
volatile UNS_32 usbreset; /* Separate reset of USB APB and I/O */
volatile UNS_32 apbwait; /* APB Bridge AHB wait state control */
} CLKSCREGS;
/* Power/state Control Status Register bits */
#define PWRSR_MCDR_BIT (6)
#define PWRSR_DCDET_BIT (7)
#define PWRSR_WUDR_BIT (8)
#define PWRSR_WUON_BIT (9)
#define PWRSR_NBFLG_BIT (10)
#define PWRSR_RSTFLG_BIT (11)
#define PWRSR_PFFLG_BIT (12)
#define PWRSR_CLDFLG_BIT (13)
#define PWRSR_LCKFLG_BIT (14)
/* #define PWRSR_RTCDIV_WIDTH (6) */
#define PWRSR_RTCDIV _BITMASK(PWRSR_MCDR_BIT)
#define PWRSR_MCDR _BIT(PWRSR_MCDR_BIT)
#define PWRSR_DCDET _BIT(PWRSR_DCDET_BIT)
#define PWRSR_WUDR _BIT(PWRSR_WUDR_BIT)
#define PWRSR_WUON _BIT(PWRSR_WUON_BIT)
#define PWRSR_NBFLG _BIT(PWRSR_NBFLG_BIT)
#define PWRSR_RSTFLG _BIT(PWRSR_RSTFLG_BIT)
#define PWRSR_PFFLG _BIT(PWRSR_PFFLG_BIT)
#define PWRSR_CLDFLG _BIT(PWRSR_CLDFLG_BIT)
#define PWRSR_LCKFLG _BIT(PWRSR_LCKFLG_BIT)
/* zzz #define PWRSR_CHIPID_WIDTH (8) */
#define PWRSR_CHIPID _SBF(16, _BITMASK(8))
/* zzz #define PWRSR_CHIPMAN_WIDTH (8) */
#define PWRSR_CHIPMAN _SBF(24, _BITMASK(8))
/* Clock/debug Control Status Register bits */
#define PWRCNT_WAKEDIS _BIT(1)
#define PWRCNT_PGMCLK_WIDTH (8)
#define PWRCNT_PGMCLK(n) _SBF(8,(n) & _BITMASK(PWRCNT_PGMCLK_WIDTH))
/* Clock Speed Control Register bits and bit fields */
#define CLKSET_MAINDIV1(n) _SBF(7, ((n) & 0x0F))
#define CLKSET_MAINDIV2(n) _SBF(11, ((n) & 0x1F))
#define CLKSET_PREDIV(n) _SBF(2, ((n) & 0x1F))
#define CLKSET_HCLKDIV1 _SBF(0, 0x00)
#define CLKSET_HCLKDIV2 _SBF(0, 0x01)
#define CLKSET_HCLKDIV3 _SBF(0, 0x02)
#define CLKSET_HCLKDIV4 _SBF(0, 0x03)
#define CLKSET_PCLKDIV2 _SBF(16, 0x0)
#define CLKSET_PCLKDIV4 _SBF(16, 0x1)
#define CLKSET_PCLKDIV8 _SBF(16, 0x2)
#define CLKSET_PS0 _SBF(18, 0x0)
#define CLKSET_PS1 _SBF(18, 0x1)
#define CLKSET_PS2 _SBF(18, 0x2)
#define CLKSET_PS3 _SBF(18, 0x3)
/* Clock USB Register bits */
#define USBRESET_IO _BIT(0)
#define USBRESET_APB _BIT(1)
/* APB wait register bits */
#define APB_NO_WRITE_WAIT _BIT(0)
/***********************************************************************
***********************************************************************
*** System Clocks
***********************************************************************
**********************************************************************/
#define LH7A400_BASE_CLOCK (14745600)
/* derived clocks */
#define CLKSC_XTAL_IN (LH7A400_BASE_CLOCK)
#define CLKSC_SSP_CLK (CLKSC_XTAL_IN / 2)
#define CLKSC_BMI_CLK (CLKSC_XTAL_IN / 2)
#define CLKSC_UART_CLK (CLKSC_XTAL_IN / 2)
#define CLKSC_DCDC_CLK (CLKSC_XTAL_IN / 5)
#define CLKSC_TIMER_SEL0_CLK (CLKSC_XTAL_IN / 7372)
#define CLKSC_TIMER_SEL1_CLK (CLKSC_XTAL_IN / 29)
#define CLKSC_TIMER3_CLK (CLKSC_XTAL_IN / 2)
#define CLKSC_AAC_CLK (CLKSC_XTAL_IN / 5)
#define CLKSC_USB_CLK ((CLKSC_XTAL_IN * 9 * 21) / (29 * 2))
/***********************************************************************
* Clock Set Codes for CLKSC->clkset register
**********************************************************************/
/*
* Use the following manifest constants to set the CPU, AHB, and APB
* clocking to the indicated frequencies.
*/
/* CPU: 33 MHz; AHB: 33 MHz; APB: 8.25 MHz (/4) */
#define CLKSET_33_33_8 (CLKSET_HCLKDIV1 | \
CLKSET_MAINDIV1(15) | \
CLKSET_MAINDIV2(8) | \
CLKSET_PREDIV(17) | \
CLKSET_PS2 | \
CLKSET_PCLKDIV4)
/* CPU: 33 MHz; AHB: 33 MHz; APB: 16.5 MHz (/2) */
#define CLKSET_33_33_16 (CLKSET_HCLKDIV1 | \
CLKSET_MAINDIV1(15) | \
CLKSET_MAINDIV2(8) | \
CLKSET_PREDIV(17) | \
CLKSET_PS2 | \
CLKSET_PCLKDIV2)
/* CPU: 50 MHz; AHB: 50 MHz; APB: 12.5 MHz (/4) */
#define CLKSET_50_50_12 (CLKSET_HCLKDIV1 | \
CLKSET_MAINDIV1(11) | \
CLKSET_MAINDIV2(10) | \
CLKSET_PREDIV(21) | \
CLKSET_PS1 | \
CLKSET_PCLKDIV4)
/* CPU: 50 MHz; AHB: 50 MHz; APB: 25 MHz (/2) */
#define CLKSET_50_50_25 (CLKSET_HCLKDIV1 | \
CLKSET_MAINDIV1(11) | \
CLKSET_MAINDIV2(10) | \
CLKSET_PREDIV(21) | \
CLKSET_PS1 | \
CLKSET_PCLKDIV2)
/* CPU: 66 MHz; AHB: 33 MHz; APB: 8.25 MHz (/4) */
#define CLKSET_66_33_8 (CLKSET_HCLKDIV2 | \
CLKSET_MAINDIV1(15) | \
CLKSET_MAINDIV2(8) | \
CLKSET_PREDIV(17) | \
CLKSET_PS1 | \
CLKSET_PCLKDIV4)
/* CPU: 66 MHz; AHB: 33 MHz; APB: 16.5 MHz (/2) */
#define CLKSET_66_33_16 (CLKSET_HCLKDIV2 | \
CLKSET_MAINDIV1(15) | \
CLKSET_MAINDIV2(8) | \
CLKSET_PREDIV(17) | \
CLKSET_PS1 | \
CLKSET_PCLKDIV2)
/* CPU: 66 MHz; AHB: 66 MHz; APB: 16.5 MHz (/4) */
#define CLKSET_66_66_16 (CLKSET_HCLKDIV1 | \
CLKSET_MAINDIV1(15) | \
CLKSET_MAINDIV2(8) | \
CLKSET_PREDIV(17) | \
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